def definition(io):
lut_list = []
lut_list.append(SB_LUT4(LUT_INIT=int('0110100110010110', 2)))
lut_list.append(SB_LUT4(LUT_INIT=int('0111111011101000', 2)))
lut_list.append(SB_LUT4(LUT_INIT=int('1000000000000000', 2)))
for i in range(3):
wire(io.I, bits([lut_list[i].I0, lut_list[i].I1, lut_list[i].I2, lut_list[i].I3]))
wire(lut_list[i].O, io.O[i])
def definition(io):
weigths_rom = ROMB(weights_list)
# using 16 LUTs to store the image, each LUT contributes 1 bit per cycle
lut_list = []
for i in range(N):
lut_list.append(SB_LUT4(LUT_INIT=imgs_list[N * image_id + i]))
wire(io.CYCLE, weigths_rom.RADDR[:n])
wire(io.IDX, weigths_rom.RADDR[n:n + b])
if n+b < 8:
wire(bits(0, 8-n-b), weigths_rom.RADDR[n+b:])
wire(1, weigths_rom.RE)
wire(weigths_rom.RDATA, io.WEIGHT)
wire(io.CLK, weigths_rom.RCLK)
for i in range(N):
wire(io.CYCLE, bits([lut_list[i].I0, lut_list[i].I1, lut_list[i].I2, lut_list[i].I3]))
wire(lut_list[i].O, io.IMAGE[i])
def definition(io):
weights_list = [1] + [2**16-1]*15 + [3] + [2**16-1]*15 + ([0] + [2**16-1]*15)*((256-32)//16)
weigths_rom = ROMB(weights_list)
lut_list = []
for i in range(N):
lut_list.append(SB_LUT4(LUT_INIT=1))
wire(io.CYCLE, weigths_rom.RADDR[:n])
wire(io.IDX, weigths_rom.RADDR[n:n+b])
if n + b < 8:
wire(bits(0, 8-n-b), weigths_rom.RADDR[n+b:])
wire(1, weigths_rom.RE)
wire(weigths_rom.RDATA, io.WEIGHT)
wire(io.CLK, weigths_rom.RCLK)
for i in range(N):
wire(io.CYCLE, bits([lut_list[i].I0, lut_list[i].I1, lut_list[i].I2, lut_list[i].I3]))
wire(lut_list[i].O, io.IMAGE[i])
def definition(io):
# IF - get cycle_id, label_index_id
controller = Controller()
reg_1_cycle = mantle.Register(n)
reg_1_control = mantle.DFF(init=1)
wire(io.CLK, controller.CLK)
wire(io.CLK, reg_1_cycle.CLK)
wire(io.CLK, reg_1_control.CLK)
reg_1_idx = controller.IDX
wire(controller.CYCLE, reg_1_cycle.I)
wire(1, reg_1_control.I)
# RR - get weight block, image block of N bits
readROM = ReadROM()
wire(reg_1_idx, readROM.IDX)
wire(reg_1_cycle.O, readROM.CYCLE)
reg_2 = mantle.Register(N + b + n)
reg_2_control = mantle.DFF()
reg_2_weight = readROM.WEIGHT
wire(io.CLK, reg_2.CLK)
wire(io.CLK, readROM.CLK)
wire(io.CLK, reg_2_control.CLK)
wire(readROM.IMAGE, reg_2.I[:N])
wire(reg_1_idx, reg_2.I[N:N + b])
wire(reg_1_cycle.O, reg_2.I[N + b:])
wire(reg_1_control.O, reg_2_control.I)
# EX - NXOr for multiplication, pop count and accumulate the result for activation
multiplier = mantle.NXOr(height=2, width=N)
bit_counter = DefineBitCounter(N)()
adder = mantle.Add(n_bc_adder, cin=False, cout=False)
mux_for_adder_0 = mantle.Mux(height=2, width=n_bc_adder)
mux_for_adder_1 = mantle.Mux(height=2, width=n_bc_adder)
reg_3_1 = mantle.Register(n_bc_adder)
reg_3_2 = mantle.Register(b + n)
wire(io.CLK, reg_3_1.CLK)
wire(io.CLK, reg_3_2.CLK)
wire(reg_2_weight, multiplier.I0)
wire(reg_2.O[:N], multiplier.I1)
wire(multiplier.O, bit_counter.I)
wire(bits(0, n_bc_adder), mux_for_adder_0.I0)
wire(bit_counter.O, mux_for_adder_0.I1[:n_bc])
if n_bc_adder > n_bc:
wire(bits(0, n_bc_adder - n_bc), mux_for_adder_0.I1[n_bc:])
# only when data read is ready (i.e. control signal is high), accumulate the pop count result
wire(reg_2_control.O, mux_for_adder_0.S)
wire(reg_3_1.O, mux_for_adder_1.I0)
wire(bits(0, n_bc_adder), mux_for_adder_1.I1)
if n == 4:
comparison_3 = SB_LUT4(LUT_INIT=int('0' * 15 + '1', 2))
wire(
reg_2.O[N + b:],
bits([
comparison_3.I0, comparison_3.I1, comparison_3.I2,
comparison_3.I3
]))
else:
comparison_3 = mantle.EQ(n)
wire(reg_2.O[N + b:], comparison_3.I0)
wire(bits(0, n), comparison_3.I1)
wire(comparison_3.O, mux_for_adder_1.S)
wire(mux_for_adder_0.O, adder.I0)
wire(mux_for_adder_1.O, adder.I1)
wire(adder.O, reg_3_1.I)
wire(reg_2.O[N:], reg_3_2.I)
# CF - classify the image
classifier = Classifier()
reg_4 = mantle.Register(n + b)
reg_4_idx = classifier.O
wire(io.CLK, classifier.CLK)
wire(io.CLK, reg_4.CLK)
wire(reg_3_1.O, classifier.I)
wire(reg_3_2.O[:b], classifier.IDX)
wire(reg_3_2.O, reg_4.I)
# WB - wait to show the result until the end
reg_5 = mantle.Register(b, has_ce=True)
comparison_5_1 = mantle.EQ(b)
comparison_5_2 = mantle.EQ(n)
and_gate = mantle.And()
wire(io.CLK, reg_5.CLK)
wire(reg_4_idx, reg_5.I)
wire(reg_4.O[:b], comparison_5_1.I0)
wire(bits(num_classes - 1, b), comparison_5_1.I1)
wire(reg_4.O[b:], comparison_5_2.I0)
wire(bits(num_cycles - 1, n), comparison_5_2.I1)
wire(comparison_5_1.O, and_gate.I0)
wire(comparison_5_2.O, and_gate.I1)
wire(and_gate.O, reg_5.CE)
wire(reg_5.O, io.O)
# latch the light indicating the end
reg_6 = mantle.DFF()
wire(io.CLK, reg_6.CLK)
or_gate = mantle.Or()
wire(and_gate.O, or_gate.I0)
wire(reg_6.O, or_gate.I1)
wire(or_gate.O, reg_6.I)
wire(reg_6.O, io.D)