def to_circuit(self, char_in):
(i, o) = self._regex.to_circuit(char_in)
orin = mantle.Or(2)
orout = mantle.Or(2)
m.wire(o, orin.I1)
m.wire(o, orout.I1)
m.wire(orin.O, i)
b = m.Bit()
m.wire(b, orin.I0)
m.wire(b, orout.I0)
return (b, orout.O)
def to_circuit(self, char_in):
(li, lo) = self._l.to_circuit(char_in)
(ri, ro) = self._l.to_circuit(char_in)
or_ = mantle.Or(2)
or_(lo, ro)
b = m.Bit()
m.wire(b, li)
m.wire(b, ri)
return (b, or_.O)
def create_connect_box():
cb = m.DefineCircuit("connect_box",
"operand0", m.In(m.Bits(1)),
"operand1", m.In(m.Bits(1)),
"result", m.Out(m.Bits(1)),
"clk", m.In(m.Clock),
"rst", m.In(m.Reset),
"config_data", m.In(m.Bits(32)),
"config_en", m.In(m.Bit))
# Configuration data
config_reg = mantle.Register(32, init=0, has_ce=True, has_reset=True)
m.wire(cb.config_data, config_reg.I)
m.wire(cb.clk, config_reg.CLK)
m.wire(cb.config_en, config_reg.CE)
rst_inv = mantle.Invert(1)
m.wire(rst_inv.I[0], cb.rst)
m.wire(rst_inv.O[0], config_reg.RESET)
# Operations in CB
and_op = mantle.And(2, 1)
m.wire(cb.operand0, and_op.I0)
m.wire(cb.operand1, and_op.I1)
or_op = mantle.Or(2, 1)
m.wire(cb.operand0, or_op.I0)
m.wire(cb.operand1, or_op.I1)
xor_op = mantle.XOr(2, 1)
m.wire(cb.operand0, xor_op.I0)
m.wire(cb.operand1, xor_op.I1)
not_op = mantle.Invert(1)
m.wire(cb.operand0, not_op.I)
# Config mux
config_mux = mantle.Mux(height=4, width=1)
m.wire(config_mux.O, cb.result)
m.wire(config_mux.S, config_reg.O[0:2])
m.wire(and_op.O, config_mux.I0)
m.wire(or_op.O, config_mux.I1)
m.wire(xor_op.O, config_mux.I2)
m.wire(not_op.O, config_mux.I3)
return cb
def definition(io):
# Configuration data
config_reg = mantle.Register(32,
init=0,
has_ce=True,
has_reset=True)
m.wire(io.config_data, config_reg.I)
m.wire(io.clk, config_reg.CLK)
m.wire(io.config_en, config_reg.CE)
rst_inv = mantle.Invert(1)
m.wire(rst_inv.I[0], io.rst)
m.wire(rst_inv.O[0], config_reg.RESET)
# Operations in CLB
and_op = mantle.And(2, 1)
m.wire(io.operand0, and_op.I0)
m.wire(io.operand1, and_op.I1)
or_op = mantle.Or(2, 1)
m.wire(io.operand0, or_op.I0)
m.wire(io.operand1, or_op.I1)
xor_op = mantle.XOr(2, 1)
m.wire(io.operand0, xor_op.I0)
m.wire(io.operand1, xor_op.I1)
not_op = mantle.Invert(1)
m.wire(io.operand0, not_op.I)
# Config mux
config_mux = mantle.Mux(height=4, width=1)
m.wire(config_mux.O, io.result)
m.wire(config_mux.S, config_reg.O[0:2])
m.wire(and_op.O, config_mux.I0)
m.wire(or_op.O, config_mux.I1)
m.wire(xor_op.O, config_mux.I2)
m.wire(not_op.O, config_mux.I3)
def definition(io):
# IF - get cycle_id, label_index_id
controller = Controller()
reg_1_cycle = mantle.Register(n)
reg_1_control = mantle.DFF(init=1)
wire(io.CLK, controller.CLK)
wire(io.CLK, reg_1_cycle.CLK)
wire(io.CLK, reg_1_control.CLK)
reg_1_idx = controller.IDX
wire(controller.CYCLE, reg_1_cycle.I)
wire(1, reg_1_control.I)
# RR - get weight block, image block of N bits
readROM = ReadROM()
wire(reg_1_idx, readROM.IDX)
wire(reg_1_cycle.O, readROM.CYCLE)
reg_2 = mantle.Register(N + b + n)
reg_2_control = mantle.DFF()
reg_2_weight = readROM.WEIGHT
wire(io.CLK, reg_2.CLK)
wire(io.CLK, readROM.CLK)
wire(io.CLK, reg_2_control.CLK)
wire(readROM.IMAGE, reg_2.I[:N])
wire(reg_1_idx, reg_2.I[N:N + b])
wire(reg_1_cycle.O, reg_2.I[N + b:])
wire(reg_1_control.O, reg_2_control.I)
# EX - NXOr for multiplication, pop count and accumulate the result for activation
multiplier = mantle.NXOr(height=2, width=N)
bit_counter = DefineBitCounter(N)()
adder = mantle.Add(n_bc_adder, cin=False, cout=False)
mux_for_adder_0 = mantle.Mux(height=2, width=n_bc_adder)
mux_for_adder_1 = mantle.Mux(height=2, width=n_bc_adder)
reg_3_1 = mantle.Register(n_bc_adder)
reg_3_2 = mantle.Register(b + n)
wire(io.CLK, reg_3_1.CLK)
wire(io.CLK, reg_3_2.CLK)
wire(reg_2_weight, multiplier.I0)
wire(reg_2.O[:N], multiplier.I1)
wire(multiplier.O, bit_counter.I)
wire(bits(0, n_bc_adder), mux_for_adder_0.I0)
wire(bit_counter.O, mux_for_adder_0.I1[:n_bc])
if n_bc_adder > n_bc:
wire(bits(0, n_bc_adder - n_bc), mux_for_adder_0.I1[n_bc:])
# only when data read is ready (i.e. control signal is high), accumulate the pop count result
wire(reg_2_control.O, mux_for_adder_0.S)
wire(reg_3_1.O, mux_for_adder_1.I0)
wire(bits(0, n_bc_adder), mux_for_adder_1.I1)
if n == 4:
comparison_3 = SB_LUT4(LUT_INIT=int('0' * 15 + '1', 2))
wire(
reg_2.O[N + b:],
bits([
comparison_3.I0, comparison_3.I1, comparison_3.I2,
comparison_3.I3
]))
else:
comparison_3 = mantle.EQ(n)
wire(reg_2.O[N + b:], comparison_3.I0)
wire(bits(0, n), comparison_3.I1)
wire(comparison_3.O, mux_for_adder_1.S)
wire(mux_for_adder_0.O, adder.I0)
wire(mux_for_adder_1.O, adder.I1)
wire(adder.O, reg_3_1.I)
wire(reg_2.O[N:], reg_3_2.I)
# CF - classify the image
classifier = Classifier()
reg_4 = mantle.Register(n + b)
reg_4_idx = classifier.O
wire(io.CLK, classifier.CLK)
wire(io.CLK, reg_4.CLK)
wire(reg_3_1.O, classifier.I)
wire(reg_3_2.O[:b], classifier.IDX)
wire(reg_3_2.O, reg_4.I)
# WB - wait to show the result until the end
reg_5 = mantle.Register(b, has_ce=True)
comparison_5_1 = mantle.EQ(b)
comparison_5_2 = mantle.EQ(n)
and_gate = mantle.And()
wire(io.CLK, reg_5.CLK)
wire(reg_4_idx, reg_5.I)
wire(reg_4.O[:b], comparison_5_1.I0)
wire(bits(num_classes - 1, b), comparison_5_1.I1)
wire(reg_4.O[b:], comparison_5_2.I0)
wire(bits(num_cycles - 1, n), comparison_5_2.I1)
wire(comparison_5_1.O, and_gate.I0)
wire(comparison_5_2.O, and_gate.I1)
wire(and_gate.O, reg_5.CE)
wire(reg_5.O, io.O)
# latch the light indicating the end
reg_6 = mantle.DFF()
wire(io.CLK, reg_6.CLK)
or_gate = mantle.Or()
wire(and_gate.O, or_gate.I0)
wire(reg_6.O, or_gate.I1)
wire(or_gate.O, reg_6.I)
wire(reg_6.O, io.D)