def __init__(self, app):
self._app = app
# Initialize the ECS architecture for this world
self._em = ecs.EntityManager(self)
self._cm = ecs.ComponentManager(self)
self._batch = memory.StaticBatch(memory.MemoryManager(300000), self)
self._loader = modeling.ModelLoader()
def __init__(self):
self.scope = 'global'
self.lastType = ''
self.functionsDir = {
'global': {
'type': 'void',
'params': [],
'vars': {}
},
}
self.memory = mem.MemoryManager()
def __init__(self, uthernet: uthernet.Uthernet):
memory_map = [
memory.MemoryRegion("Zero page", 0x0000, 0x00ff),
memory.MemoryRegion("Stack", 0x0100, 0x01ff),
memory.MemoryRegion(
"Text page 1",
0x0400,
0x7ff,
write_interceptor=self.TextPageWriteInterceptor),
memory.MemoryRegion("HiRes Page 1", 0x2000, 0x2fff),
memory.MemoryRegion("HiRes Page 2", 0x4000, 0x4fff,
writable=False),
memory.MemoryRegion("IO page",
0xc000,
0xc0ff,
read_interceptor=self.io_interceptor,
write_interceptor=self.io_interceptor),
memory.MemoryRegion("Slot 1 ROM", 0xc100, 0xc1ff, writable=False),
memory.MemoryRegion("Slot 2 ROM", 0xc200, 0xc2ff, writable=False),
memory.MemoryRegion("Slot 3 ROM", 0xc300, 0xc3ff, writable=False),
memory.MemoryRegion("Slot 4 ROM", 0xc400, 0xc4ff, writable=False),
memory.MemoryRegion("Slot 5 ROM", 0xc500, 0xc5ff, writable=False),
memory.MemoryRegion("Slot 6 ROM", 0xc600, 0xc6ff, writable=False),
memory.MemoryRegion("Slot 7 ROM", 0xc700, 0xc7ff, writable=False),
memory.MemoryRegion("ROM",
0xd000,
0xffff,
entrypoints={
0xf3e2:
machine._Event("ROM", "HGR"),
0xfca8:
self._Wait,
0xfded:
machine._Event("ROM", "COUT"),
0xfe89:
machine._Event(
"ROM", "Select the keyboard (IN#0)")
},
writable=False)
]
self.memory_manager = memory.MemoryManager(memory_map)
self.memory = self.memory_manager.memory
self.cpu = mpu65c02.MPU(memory=self.memory)
self.uthernet = uthernet # type: uthernet.Uthernet
self.disassembler = disassembler.Disassembler(self.cpu)
def _uther_wmode(mode, value):
if mode & machine.AccessMode.READ:
return self.uthernet.read_mode()
else:
return self.uthernet.write_mode(value)
def _uther_wadrh(mode, value):
old = self.uthernet.ptr
self.uthernet.ptr = (value << 8) | (self.uthernet.ptr & 0x7f)
machine.Log("WADRH", "%04x -> %04x" % (old, self.uthernet.ptr))
def _uther_wadrl(mode, value):
old = self.uthernet.ptr
self.uthernet.ptr = (self.uthernet.ptr & 0x7f00) | value
machine.Log("WADRL", "%04x -> %04x" % (old, self.uthernet.ptr))
def _uther_wdata(mode, value):
if mode & machine.AccessMode.READ:
return self.uthernet.read_data()
else:
return self.uthernet.write_data(value)
def _tick(mode, value):
machine.Log("Tick", self.cpu.processorCycles)
# Set up interceptors for accessing various interesting parts of the
# memory map
self.io_map = {
0xc030: (machine.AccessMode.RW, "TICK", _tick),
0xc094: (machine.AccessMode.RW, "WMODE", _uther_wmode),
0xc095: (machine.AccessMode.WRITE, "WADRH", _uther_wadrh),
0xc096: (machine.AccessMode.WRITE, "WADRL", _uther_wadrl),
0xc097: (machine.AccessMode.RW, "WDATA", _uther_wdata),
}
self.soft_switches = {}
for ss in [
machine.SoftSwitch("80Store",
clear_addr=0xc000,
set_addr=0xc001,
status_addr=0xc018,
callback=machine.SoftSwitch.unimplemented),
machine.SoftSwitch("RamRd",
clear_addr=0xc002,
set_addr=0xc003,
status_addr=0xc013,
callback=machine.SoftSwitch.unimplemented),
machine.SoftSwitch("RamWrt",
clear_addr=0xc004,
set_addr=0xc005,
status_addr=0xc014,
callback=machine.SoftSwitch.unimplemented),
machine.SoftSwitch("IntCxROM",
clear_addr=0xc006,
set_addr=0xc007,
status_addr=0xc015,
callback=machine.SoftSwitch.unimplemented),
machine.SoftSwitch("AltZP",
clear_addr=0xc008,
set_addr=0xc009,
status_addr=0xc016,
callback=machine.SoftSwitch.unimplemented),
machine.SoftSwitch("SlotC3ROM",
clear_addr=0xc00a,
set_addr=0xc00b,
status_addr=0xc017,
callback=machine.SoftSwitch.unimplemented),
machine.SoftSwitch("80Col",
clear_addr=0xc00c,
set_addr=0xc00d,
status_addr=0xc01f),
machine.SoftSwitch("AltCharSet",
clear_addr=0xc00e,
set_addr=0xc00f,
status_addr=0xc01e),
machine.SoftSwitch("Text",
clear_addr=0xc050,
set_addr=0xc051,
status_addr=0xc01a,
mode=machine.AccessMode.RW),
machine.SoftSwitch("Mixed",
clear_addr=0xc052,
set_addr=0xc053,
status_addr=0xc01b,
mode=machine.AccessMode.RW),
machine.SoftSwitch("Page2",
clear_addr=0xc054,
set_addr=0xc055,
status_addr=0xc01c,
mode=machine.AccessMode.RW),
machine.SoftSwitch("Hires",
clear_addr=0xc056,
set_addr=0xc057,
status_addr=0xc01d,
mode=machine.AccessMode.RW)
]:
self.soft_switches[ss.name] = ss
ss.register(self.io_map)
def __init__(self):
memory_map = [
memory.MemoryRegion("Zero page", 0x0000, 0x00ff),
memory.MemoryRegion("Stack", 0x0100, 0x01ff),
memory.MemoryRegion(
"Text page 1",
0x0400,
0x7ff,
write_interceptor=self.TextPageWriteInterceptor),
memory.MemoryRegion("IO page",
0xc000,
0xc0ff,
read_interceptor=self.IOInterceptor,
write_interceptor=self.IOInterceptor),
memory.MemoryRegion("Slot 1 ROM", 0xc100, 0xc1ff, writable=False),
memory.MemoryRegion("Slot 2 ROM", 0xc200, 0xc2ff, writable=False),
memory.MemoryRegion("Slot 3 ROM", 0xc300, 0xc3ff, writable=False),
memory.MemoryRegion("Slot 4 ROM", 0xc400, 0xc4ff, writable=False),
memory.MemoryRegion("Slot 5 ROM", 0xc500, 0xc5ff, writable=False),
memory.MemoryRegion("Slot 6 ROM",
0xc600,
0xc6ff,
entrypoints={0xc65c: self._ReadDiskSector},
writable=False),
memory.MemoryRegion("Slot 7 ROM", 0xc700, 0xc7ff, writable=False),
memory.MemoryRegion("ROM",
0xd000,
0xffff,
entrypoints={
0xfca8:
self._Wait,
0xfe89:
_Event("ROM", "Select the keyboard (IN#0)")
},
writable=False)
]
self.memory_manager = memory.MemoryManager(memory_map)
self.memory = self.memory_manager.memory
self.cpu = mpu65c02.MPU(memory=self.memory)
# Set up interceptors for accessing various interesting parts of the memory map
self.io_map = {
0xc007: (MODE_WRITE, "Turn CXROM switch on"),
0xc015: (MODE_READ, "Status of Peripheral/CXROM Access"),
0xc051: (MODE_READ, "Display text"),
0xc054: (MODE_READ, "Text page 1"),
0xc056: (MODE_READ, "Enter lores mode"),
# Slot 6 Disk II
0xc0e0: (MODE_READ, "phase 0 off"),
0xc0e1: (MODE_READ, "phase 0 on"),
0xc0e2: (MODE_READ, "phase 1 off"),
0xc0e3: (MODE_READ, "phase 1 on"),
0xc0e4: (MODE_READ, "phase 2 off"),
0xc0e5: (MODE_READ, "phase 2 on"),
0xc0e6: (MODE_READ, "phase 3 off"),
0xc0e7: (MODE_READ, "phase 3 on"),
0xc0e8: (MODE_READ, "Drives off"),
0xc0e9: (MODE_READ, "Selected drive on"),
0xc0ea: (MODE_READ, "Select drive 1"),
0xc0eb: (MODE_READ, "Select drive 2"),
0xc0ec: (MODE_READ, "Shift while writing/read data"),
0xc0ed: (MODE_READ, "Shift while writing/read data"),
0xc0ee: (MODE_READ, "Enabling disk read mode."),
0xc0ef: (MODE_READ, "Enabling disk write mode."),
}
def __init__(self, stream: bytes):
memory_map = [
memory.MemoryRegion("Registers",
0x0000,
0x002f,
read_interceptor=self.io_interceptor,
write_interceptor=self.io_interceptor),
memory.MemoryRegion("Socket registers",
0x0400,
0x07ff,
read_interceptor=self.io_interceptor,
write_interceptor=self.io_interceptor),
memory.MemoryRegion("TX Memory", 0x4000, 0x5fff),
memory.MemoryRegion("RX Memory", 0x6000, 0x7fff),
]
self.memory_manager = memory.MemoryManager(memory_map)
self.memory = self.memory_manager.memory
self.memory_manager.enable()
self._indirect_bus_mode = False # type: bool
self._auto_increment = False # type: bool
# Address read pointer
self.ptr = 0x0000
# Inbound data to buffer via TCP socket
self.stream = stream
def _mode(mode, value):
if not (mode & machine.AccessMode.WRITE):
return
# 7 - reset
# 1 - address auto-increment
# 0 - indirect bus mode
assert value & 0b10000011 == value, value
self._indirect_bus_mode = bool(value & 1)
self._auto_increment = bool(value & (1 << 1))
machine.Log(
"Uthernet", "Indirect bus mode: %s, Auto-incr: %s" %
(self._indirect_bus_mode, self._auto_increment))
if value & (1 << 7):
self.reset()
def _socket_mode(mode, value):
if not (mode & machine.AccessMode.WRITE):
return
# 5 - delayed ACK disabled
# 3 - 0 for TCP
# 2 - 0 for TCP
# 1 - 0 for TCP
# 0 - 1 for TCP
assert value == 0b100001, value
def _socket_command(mode, value):
if not (mode & machine.AccessMode.WRITE):
return
def _OPEN():
# Move TCP status to SOCK_INIT
self.memory[0x403] = 0x13
machine.Log("Uthernet", "Opening socket 0")
def _CONNECT():
# Move TCP status to SOCK_ESTABLISHED
self.memory[0x403] = 0x17
def _RECV():
raise NotImplementedError
commands = {
0x01: _OPEN,
# 0x02: _LISTEN,
0x04: _CONNECT,
# 0x08: _DISCON,
# 0x10: _CLOSE,
# 0x20: _SEND,
# 0x21: _SEND_MAC,
# 0x22: _SEND_KEEP,
0x40: _RECV,
}
handler = commands.get(value)
if handler:
handler()
self.io_map = {
# CONTROL REGISTERS
0x0000: (machine.AccessMode.RW, "Mode", _mode),
0x0001: (machine.AccessMode.RW, "Gateway Address 0", None),
0x0002: (machine.AccessMode.RW, "Gateway Address 1", None),
0x0003: (machine.AccessMode.RW, "Gateway Address 2", None),
0x0004: (machine.AccessMode.RW, "Gateway Address 3", None),
0x0005: (machine.AccessMode.RW, "Subnet Mask Address 0", None),
0x0006: (machine.AccessMode.RW, "Subnet Mask Address 1", None),
0x0007: (machine.AccessMode.RW, "Subnet Mask Address 2", None),
0x0008: (machine.AccessMode.RW, "Subnet Mask Address 3", None),
0x0009: (machine.AccessMode.RW, "Source Hardware Address 0", None),
0x000a: (machine.AccessMode.RW, "Source Hardware Address 1", None),
0x000b: (machine.AccessMode.RW, "Source Hardware Address 2", None),
0x000c: (machine.AccessMode.RW, "Source Hardware Address 3", None),
0x000d: (machine.AccessMode.RW, "Source Hardware Address 4", None),
0x000e: (machine.AccessMode.RW, "Source Hardware Address 5", None),
0x000f: (machine.AccessMode.RW, "Source IP Address 0", None),
0x0010: (machine.AccessMode.RW, "Source IP Address 1", None),
0x0011: (machine.AccessMode.RW, "Source IP Address 2", None),
0x0012: (machine.AccessMode.RW, "Source IP Address 3", None),
0x0015: (machine.AccessMode.RW, "Interrupt",
self.unimplemented_io_callback),
0x0016: (machine.AccessMode.RW, "Interrupt Mask",
self.unimplemented_io_callback),
0x0017: (machine.AccessMode.RW, "Retry Time 0",
self.unimplemented_io_callback),
0x0018: (machine.AccessMode.RW, "Retry Time 1",
self.unimplemented_io_callback),
0x0019: (machine.AccessMode.RW, "Retry Count",
self.unimplemented_io_callback),
0x001a: (machine.AccessMode.RW, "RX Memory Size", None),
0x001b: (machine.AccessMode.RW, "TX Memory Size", None),
0x001c: (machine.AccessMode.RW, "PPPoE Auth Type 0",
self.unimplemented_io_callback),
0x001d: (machine.AccessMode.RW, "PPPoE Auth Type 1",
self.unimplemented_io_callback),
0x0028: (machine.AccessMode.RW, "PPP LCP Request Timer",
self.unimplemented_io_callback),
0x0029: (machine.AccessMode.RW, "PPP LCP Magic Number",
self.unimplemented_io_callback),
0x002a: (machine.AccessMode.RW, "Unreachable IP Address 0",
self.unimplemented_io_callback),
0x002b: (machine.AccessMode.RW, "Unreachable IP Address 1",
self.unimplemented_io_callback),
0x002c: (machine.AccessMode.RW, "Unreachable IP Address 2",
self.unimplemented_io_callback),
0x002d: (machine.AccessMode.RW, "Unreachable IP Address 3",
self.unimplemented_io_callback),
0x002e: (machine.AccessMode.RW, "Unreachable Port 0",
self.unimplemented_io_callback),
0x002f: (machine.AccessMode.RW, "Unreachable Port 0",
self.unimplemented_io_callback),
# SOCKET 0 registers
0x0400: (machine.AccessMode.RW, "Socket 0 Mode", _socket_mode),
0x0401:
(machine.AccessMode.RW, "Socket 0 Command", _socket_command),
0x0402: (machine.AccessMode.RW, "Socket 0 Interrupt",
self.unimplemented_io_callback),
0x0403: (machine.AccessMode.RW, "Socket 0 Status", None),
0x0404: (machine.AccessMode.RW, "Socket 0 Source Port 0", None),
0x0405: (machine.AccessMode.RW, "Socket 0 Source Port 1", None),
0x0406: (machine.AccessMode.RW, "Socket 0 Dest HW Addr 0",
self.unimplemented_io_callback),
0x0407: (machine.AccessMode.RW, "Socket 0 Dest HW Addr 1",
self.unimplemented_io_callback),
0x0408: (machine.AccessMode.RW, "Socket 0 Dest HW Addr 2",
self.unimplemented_io_callback),
0x0409: (machine.AccessMode.RW, "Socket 0 Dest HW Addr 3",
self.unimplemented_io_callback),
0x040a: (machine.AccessMode.RW, "Socket 0 Dest HW Addr 4",
self.unimplemented_io_callback),
0x040b: (machine.AccessMode.RW, "Socket 0 Dest HW Addr 5",
self.unimplemented_io_callback),
0x040c: (machine.AccessMode.RW, "Socket 0 Dest IP Addr 0", None),
0x040d: (machine.AccessMode.RW, "Socket 0 Dest IP Addr 1", None),
0x040e: (machine.AccessMode.RW, "Socket 0 Dest IP Addr 2", None),
0x040f: (machine.AccessMode.RW, "Socket 0 Dest IP Addr 3", None),
0x0410: (machine.AccessMode.RW, "Socket 0 Dest Port 0", None),
0x0411: (machine.AccessMode.RW, "Socket 0 Dest Port 1", None),
0x0412: (machine.AccessMode.RW, "Socket 0 MSS 0",
self.unimplemented_io_callback),
0x0413: (machine.AccessMode.RW, "Socket 0 MSS 1",
self.unimplemented_io_callback),
0x0414: (machine.AccessMode.RW, "Socket 0 Protocol",
self.unimplemented_io_callback),
0x0415: (machine.AccessMode.RW, "Socket 0 IP TOS",
self.unimplemented_io_callback),
0x0416: (machine.AccessMode.RW, "Socket 0 IP TTL",
self.unimplemented_io_callback),
0x0420: (machine.AccessMode.RW, "Socket 0 TX Free Size 0",
self.unimplemented_io_callback),
0x0421: (machine.AccessMode.RW, "Socket 0 TX Free Size 1",
self.unimplemented_io_callback),
0x0422: (machine.AccessMode.RW, "Socket 0 TX Read Ptr 0",
self.unimplemented_io_callback),
0x0423: (machine.AccessMode.RW, "Socket 0 TX Read Ptr 1",
self.unimplemented_io_callback),
0x0424: (machine.AccessMode.RW, "Socket 0 TX Write Ptr 0",
self.unimplemented_io_callback),
0x0425: (machine.AccessMode.RW, "Socket 0 TX Write Ptr 1",
self.unimplemented_io_callback),
0x0426:
(machine.AccessMode.RW, "Socket 0 RX Received Size 0", None),
0x0427:
(machine.AccessMode.RW, "Socket 0 RX Received Size 1", None),
0x0428: (machine.AccessMode.RW, "Socket 0 RX Read Ptr 0", None),
0x0429: (machine.AccessMode.RW, "Socket 0 RX Read Ptr 1", None),
}