def divert(self, index, candidates): out = [] for candidate in candidates: cls, name, bases, dct, fields = candidate cond1 = [f for f in fields if f.fname == "cond1"] assert (len(cond1) == 1) cond1 = cond1.pop() mm = self.mn_mod[cond1.value] for value, new_name in enumerate(mm): nfields = fields[:] s = cpu.int2bin(value, self.args['l']) args = dict(self.args) args.update({'strbits': s}) f = cpu.bs(**args) nfields[index] = f ndct = dict(dct) ndct['name'] = name + new_name out.append((cls, new_name, bases, ndct, nfields)) return out
def divert(self, index, candidates): out = [] for candidate in candidates: cls, name, bases, dct, fields = candidate cond1 = [f for f in fields if f.fname == "cond1"] assert(len(cond1) == 1) cond1 = cond1.pop() mm = self.mn_mod[cond1.value] for value, new_name in enumerate(mm): nfields = fields[:] s = cpu.int2bin(value, self.args['l']) args = dict(self.args) args.update({'strbits': s}) f = cpu.bs(**args) nfields[index] = f ndct = dict(dct) ndct['name'] = name + new_name out.append((cls, new_name, bases, ndct, nfields)) return out
index += v self.expr = regs.regs_cpr0_expr[index] return True def encode(self): e = self.expr if not e in regs.regs_cpr0_expr: return False index = regs.regs_cpr0_expr.index(e) self.value = index & 7 index >>= 2 self.parent.cpr0.value = index return True rs = cpu.bs(l=5, cls=(mips32_gpreg, )) rt = cpu.bs(l=5, cls=(mips32_gpreg, )) rd = cpu.bs(l=5, cls=(mips32_gpreg, )) ft = cpu.bs(l=5, cls=(mips32_fltpreg, )) fs = cpu.bs(l=5, cls=(mips32_fltpreg, )) fd = cpu.bs(l=5, cls=(mips32_fltpreg, )) s16imm = cpu.bs(l=16, cls=(mips32_s16imm, )) u16imm = cpu.bs(l=16, cls=(mips32_u16imm, )) s09imm = cpu.bs(l=9, cls=(mips32_s09imm, )) sa = cpu.bs(l=5, cls=(mips32_u16imm, )) base = cpu.bs(l=5, cls=(mips32_dreg_imm, )) soff = cpu.bs(l=16, cls=(mips32_soff, )) oper = cpu.bs(l=5, cls=(mips32_u16imm, )) cpr0 = cpu.bs(l=5, cls=(mips32_imm, ), fname="cpr0")
def decode(self, v): index = int(self.parent.cpr0.expr) << 3 index += v self.expr = regs.regs_cpr0_expr[index] return True def encode(self): e = self.expr if not e in regs.regs_cpr0_expr: return False index = regs.regs_cpr0_expr.index(e) self.value = index & 7 index >>=2 self.parent.cpr0.value = index return True rs = cpu.bs(l=5, cls=(mips32_gpreg,)) rt = cpu.bs(l=5, cls=(mips32_gpreg,)) rd = cpu.bs(l=5, cls=(mips32_gpreg,)) ft = cpu.bs(l=5, cls=(mips32_fltpreg,)) fs = cpu.bs(l=5, cls=(mips32_fltpreg,)) fd = cpu.bs(l=5, cls=(mips32_fltpreg,)) s16imm = cpu.bs(l=16, cls=(mips32_s16imm,)) u16imm = cpu.bs(l=16, cls=(mips32_u16imm,)) sa = cpu.bs(l=5, cls=(mips32_u16imm,)) base = cpu.bs(l=5, cls=(mips32_dreg_imm,)) soff = cpu.bs(l=16, cls=(mips32_soff,)) cpr0 = cpu.bs(l=5, cls=(mips32_imm,), fname="cpr0") cpr = cpu.bs(l=3, cls=(mips32_cpr,))
def decode(self, v): index = int(self.parent.cpr0.expr) << 3 index += v self.expr = regs.regs_cpr0_expr[index] return True def encode(self): e = self.expr if not e in regs.regs_cpr0_expr: return False index = regs.regs_cpr0_expr.index(e) self.value = index & 7 index >>=2 self.parent.cpr0.value = index return True rs = cpu.bs(l=5, cls=(mips32_gpreg,)) rt = cpu.bs(l=5, cls=(mips32_gpreg,)) rd = cpu.bs(l=5, cls=(mips32_gpreg,)) ft = cpu.bs(l=5, cls=(mips32_fltpreg,)) fs = cpu.bs(l=5, cls=(mips32_fltpreg,)) fd = cpu.bs(l=5, cls=(mips32_fltpreg,)) s16imm = cpu.bs(l=16, cls=(mips32_s16imm,)) u16imm = cpu.bs(l=16, cls=(mips32_u16imm,)) sa = cpu.bs(l=5, cls=(mips32_u16imm,)) base = cpu.bs(l=5, cls=(mips32_dreg_imm,)) soff = cpu.bs(l=16, cls=(mips32_soff,)) cpr0 = cpu.bs(l=5, cls=(mips32_imm,), fname="cpr0") cpr = cpu.bs(l=3, cls=(mips32_cpr,))