def __init__(self):
pads = Signal(8)
self.submodules.gp = Gpio(pads)
self.comb += pads[4:].eq(pads[:4])
self.submodules.wb = Wishbone()
self.submodules.dut = Master([
(self.gp, 0x00000100, 0xffffff00),
# (self.dds, 0x00010000, 0xffff0000),
(self.wb, 0x20000000, 0xe0000000),
# (self.spi, 0x40000000, 0xe0000000),
# (self.i2c, 0x60000000, 0xe0000000),
])
self.submodules.csrbanks = csrgen.BankArray(
self, lambda name, mem: {"dut": 0}[name])
self.submodules.ini = csr.Initiator(_test_gen())
self.submodules.con = csr.Interconnect(self.ini.bus,
self.csrbanks.get_buses())
#self.submodules.wbini = wishbone.Initiator(_test_gen_wb())
#self.submodules.wbtap = wishbone.Tap(self.dut.bus)
#self.submodules.wbcon = wishbone.InterconnectPointToPoint(
# self.wbini.bus, self.dut.bus)
self.submodules.wbtg = wishbone.Target(wishbone.TargetModel())
self.submodules.wbtap = wishbone.Tap(self.wbtg.bus)
self.submodules.wbic = wishbone.InterconnectPointToPoint(
self.wb.bus, self.wbtg.bus)
def __init__(self):
self.prx = TIProxy()
self.l_0_ovr = Signal()
self.leds_v = Signal(3)
self.submodules.leds = LED_outputs(self.leds_v, [[self.l_0_ovr], [0], [1]])
self.submodules.ini = Initiator(self.prx._ini_iterator())
self.submodules.ba = csrgen.BankArray(self, lambda name, _: 0)
self.submodules.incon = Interconnect(self.ini.bus, self.ba.get_buses())
self._gen = None
def do_finalize(self):
registered_mems = {regions[0] for regions in self._memory_regions}
if self.cpu_type != "none":
for mem in "rom", "sram":
if mem not in registered_mems:
raise FinalizeError(
"CPU needs a {} to be registered with SoC.register_mem()"
.format(mem))
# Wishbone
self.submodules.wishbonecon = wishbone.InterconnectShared(
self._wb_masters, self._wb_slaves, register=True)
# CSR
if self.with_csr:
self.submodules.csrbankarray = csrgen.BankArray(
self,
lambda name, memory: self.csr_map[name
if memory is None else name +
"_" + memory.name_override],
data_width=self.csr_data_width,
address_width=self.csr_address_width)
self.submodules.csrcon = csr.Interconnect(
self.wishbone2csr.csr, self.csrbankarray.get_buses())
for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
self.add_csr_region(name,
(self.mem_map["csr"] + 0x800 * mapaddr)
| self.shadow_base, self.csr_data_width,
csrs)
for name, memory, mapaddr, mmap in self.csrbankarray.srams:
self.add_csr_region(name + "_" + memory.name_override,
(self.mem_map["csr"] + 0x800 * mapaddr)
| self.shadow_base, self.csr_data_width,
memory)
# Interrupts
if hasattr(self.cpu_or_bridge, "interrupt"):
for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
if hasattr(self, k):
self.comb += self.cpu_or_bridge.interrupt[v].eq(
getattr(self, k).ev.irq)