def main():
# Compute filter coefficients with SciPy.
coef = signal.remez(80, [0, 0.1, 0.1, 0.5], [1, 0])
fir = FIR(coef)
# Simulate for different frequencies and concatenate
# the results.
in_signals = []
out_signals = []
for frequency in [0.05, 0.07, 0.1, 0.15, 0.2]:
tb = TB(fir, frequency)
fragment = autofragment.from_local()
sim = Simulator(fragment, Runner())
sim.run(100)
in_signals += tb.inputs
out_signals += tb.outputs
# Plot data from the input and output waveforms.
plt.plot(in_signals)
plt.plot(out_signals)
plt.show()
# Print the Verilog source for the filter.
print(verilog.convert(fir.get_fragment(),
ios={fir.i, fir.o}))
def get():
MHz = 1000000
clk_freq = 80*MHz
sram_size = 4096 # in kilobytes
clkfx_sys = clkfx.ClkFX(50*MHz, clk_freq)
reset0 = m1reset.M1Reset()
cpu0 = lm32.LM32()
norflash0 = norflash.NorFlash(25, 12)
sram0 = sram.SRAM(sram_size//4)
wishbone2csr0 = wishbone2csr.WB2CSR()
wishbonecon0 = wishbone.InterconnectShared(
[cpu0.ibus, cpu0.dbus],
[(0, norflash0.bus), (1, sram0.bus), (3, wishbone2csr0.wishbone)],
register=True,
offset=1)
uart0 = uart.UART(0, clk_freq, baud=115200)
csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface])
frag = autofragment.from_local()
src_verilog, vns = verilog.convert(frag,
{clkfx_sys.clkin, reset0.trigger_reset},
name="soc",
clk_signal=clkfx_sys.clkout,
rst_signal=reset0.sys_rst,
return_ns=True)
src_ucf = constraints.get(vns, clkfx_sys, reset0, norflash0, uart0)
return (src_verilog, src_ucf)
def test_asmi():
print("*** ASMI test")
# Create a hub with one port for our initiator.
hub = asmibus.Hub(32, 32)
port = hub.get_port()
hub.finalize()
# Create the initiator, target and tap (similar to the Wishbone case).
master = asmibus.Initiator(my_generator(), port)
slave = asmibus.Target(MyModelASMI(), hub)
tap = asmibus.Tap(hub)
# Run the simulation (same as the Wishbone case).
def end_simulation(s):
s.interrupt = master.done
fragment = autofragment.from_local() + Fragment(sim=[end_simulation])
sim = Simulator(fragment)
sim.run()
def main(): # The "wishbone.Initiator" library component runs our generator # and manipulates the bus signals accordingly. master = wishbone.Initiator(my_generator()) # Our slave. slave = MyPeripheral() # The "wishbone.Tap" library component examines the bus at the slave port # and displays the transactions on the console (<TRead...>/<TWrite...>). tap = wishbone.Tap(slave.bus) # Connect the master to the slave. intercon = wishbone.InterconnectPointToPoint(master.bus, slave.bus) # A small extra simulation function to terminate the process when # the initiator is done (i.e. our generator is exhausted). def end_simulation(s): s.interrupt = master.done fragment = autofragment.from_local() + Fragment(sim=[end_simulation]) sim = Simulator(fragment, Runner()) sim.run()
def test_asmi():
print("*** ASMI test")
# Create a hub with one port for our initiator.
hub = asmibus.Hub(32, 32)
port = hub.get_port()
hub.finalize()
# Create the initiator, target and tap (similar to the Wishbone case).
master = asmibus.Initiator(port, my_generator())
slave = asmibus.Target(hub, MyModelASMI())
tap = asmibus.Tap(hub)
# Run the simulation (same as the Wishbone case).
def end_simulation(s):
s.interrupt = master.done
fragment = autofragment.from_local() + Fragment(sim=[end_simulation])
sim = Simulator(fragment, Runner())
sim.run()
def main():
# The "wishbone.Initiator" library component runs our generator
# and manipulates the bus signals accordingly.
master = wishbone.Initiator(my_generator())
# Our slave.
slave = MyPeripheral()
# The "wishbone.Tap" library component examines the bus at the slave port
# and displays the transactions on the console (<TRead...>/<TWrite...>).
tap = wishbone.Tap(slave.bus)
# Connect the master to the slave.
intercon = wishbone.InterconnectPointToPoint(master.bus, slave.bus)
# A small extra simulation function to terminate the process when
# the initiator is done (i.e. our generator is exhausted).
def end_simulation(s):
s.interrupt = master.done
fragment = autofragment.from_local() + Fragment(sim=[end_simulation])
sim = Simulator(fragment, Runner())
sim.run()
def main():
# Compute filter coefficients with SciPy.
coef = signal.remez(80, [0, 0.1, 0.1, 0.5], [1, 0])
fir = FIR(coef)
# Simulate for different frequencies and concatenate
# the results.
in_signals = []
out_signals = []
for frequency in [0.05, 0.07, 0.1, 0.15, 0.2]:
tb = TB(fir, frequency)
fragment = autofragment.from_local()
sim = Simulator(fragment, Runner())
sim.run(100)
in_signals += tb.inputs
out_signals += tb.outputs
# Plot data from the input and output waveforms.
plt.plot(in_signals)
plt.plot(out_signals)
plt.show()
# Print the Verilog source for the filter.
print(verilog.convert(fir.get_fragment(), ios={fir.i, fir.o}))
