def __init__(self, platform):
self.pll_reset = CSRStorage(reset=1)
self.pll_locked = CSRStatus()
self.clock_domains.cd_rtio = ClockDomain()
self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
if platform.hw_rev == "v2.0":
clk_synth = platform.request("cdr_clk_clean_fabric")
else:
clk_synth = platform.request("si5324_clkout_fabric")
clk_synth_se = Signal()
platform.add_period_constraint(clk_synth.p, 8.0)
self.specials += [
Instance("IBUFGDS",
p_DIFF_TERM="TRUE",
p_IBUF_LOW_PWR="FALSE",
i_I=clk_synth.p,
i_IB=clk_synth.n,
o_O=clk_synth_se),
]
pll_locked = Signal()
rtio_clk = Signal()
rtiox4_clk = Signal()
fb_clk = Signal()
self.specials += [
Instance(
"PLLE2_ADV",
p_STARTUP_WAIT="FALSE",
o_LOCKED=pll_locked,
p_BANDWIDTH="HIGH",
p_REF_JITTER1=0.001,
p_CLKIN1_PERIOD=8.0,
p_CLKIN2_PERIOD=8.0,
i_CLKIN2=clk_synth_se,
# Warning: CLKINSEL=0 means CLKIN2 is selected
i_CLKINSEL=0,
# VCO @ 1.5GHz when using 125MHz input
p_CLKFBOUT_MULT=12,
p_DIVCLK_DIVIDE=1,
i_CLKFBIN=fb_clk,
i_RST=self.pll_reset.storage,
o_CLKFBOUT=fb_clk,
p_CLKOUT0_DIVIDE=3,
p_CLKOUT0_PHASE=0.0,
o_CLKOUT0=rtiox4_clk,
p_CLKOUT1_DIVIDE=12,
p_CLKOUT1_PHASE=0.0,
o_CLKOUT1=rtio_clk),
Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
MultiReg(pll_locked, self.pll_locked.status)
]
def __init__(self, platform, rtio_internal_clk, use_sma=True):
self._clock_sel = CSRStorage()
self._pll_reset = CSRStorage(reset=1)
self._pll_locked = CSRStatus()
self.clock_domains.cd_rtio = ClockDomain()
self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
# 100 MHz when using 125MHz input
self.clock_domains.cd_ext_clkout = ClockDomain(reset_less=True)
platform.add_period_constraint(self.cd_ext_clkout.clk, 5.0)
if use_sma:
ext_clkout = platform.request("user_sma_gpio_p_33")
self.sync.ext_clkout += ext_clkout.eq(~ext_clkout)
rtio_external_clk = Signal()
if use_sma:
user_sma_clock = platform.request("user_sma_clock")
platform.add_period_constraint(user_sma_clock.p, 8.0)
self.specials += Instance("IBUFDS",
i_I=user_sma_clock.p, i_IB=user_sma_clock.n,
o_O=rtio_external_clk)
pll_locked = Signal()
rtio_clk = Signal()
rtiox4_clk = Signal()
ext_clkout_clk = Signal()
self.specials += [
Instance("PLLE2_ADV",
p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
p_REF_JITTER1=0.01,
p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
i_CLKIN1=rtio_internal_clk, i_CLKIN2=rtio_external_clk,
# Warning: CLKINSEL=0 means CLKIN2 is selected
i_CLKINSEL=~self._clock_sel.storage,
# VCO @ 1GHz when using 125MHz input
p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
i_CLKFBIN=self.cd_rtio.clk,
i_RST=self._pll_reset.storage,
o_CLKFBOUT=rtio_clk,
p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
o_CLKOUT0=rtiox4_clk,
p_CLKOUT1_DIVIDE=5, p_CLKOUT1_PHASE=0.0,
o_CLKOUT1=ext_clkout_clk),
Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
Instance("BUFG", i_I=ext_clkout_clk, o_O=self.cd_ext_clkout.clk),
AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
MultiReg(pll_locked, self._pll_locked.status)
]
def __init__(self, platform, core_config):
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
# # #
self.stop = Signal()
# clk / rst
clk = platform.request("clk")
rst = platform.request("rst")
# power on reset
por_count = Signal(16, reset=2**16 - 1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(ClockSignal())
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# pll
self.submodules.pll = pll = ECP5PLL()
pll.register_clkin(clk, core_config["input_clk_freq"])
pll.create_clkout(self.cd_sys2x_i, 2 * core_config["sys_clk_freq"])
pll.create_clkout(self.cd_init, core_config["init_clk_freq"])
self.specials += [
Instance("ECLKSYNCB",
i_ECLKI=self.cd_sys2x_i.clk,
i_STOP=self.stop,
o_ECLKO=self.cd_sys2x.clk),
Instance("CLKDIVF",
p_DIV="2.0",
i_ALIGNWD=0,
i_CLKI=self.cd_sys2x.clk,
i_RST=self.cd_sys2x.rst,
o_CDIVX=self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_init,
~por_done | ~pll.locked | rst),
AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | rst),
]
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
# # #
self.stop = Signal()
# Clk / Rst
clk100 = platform.request("clk100")
rst_n = platform.request("rst_n")
platform.add_period_constraint(clk100, 1e9/100e6)
# Power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(ClockSignal())
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# PLL
self.submodules.pll = pll = ECP5PLL()
pll.register_clkin(clk100, 100e6)
pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
pll.create_clkout(self.cd_init, 25e6)
self.specials += [
Instance("ECLKSYNCB",
i_ECLKI = self.cd_sys2x_i.clk,
i_STOP = self.stop,
o_ECLKO = self.cd_sys2x.clk),
Instance("CLKDIVF",
p_DIV = "2.0",
i_ALIGNWD = 0,
i_CLKI = self.cd_sys2x.clk,
i_RST = self.cd_sys2x.rst,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | ~rst_n),
AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n)
]
def __init__(self, platform, rtio_internal_clk):
self._clock_sel = CSRStorage()
self._pll_reset = CSRStorage(reset=1)
self._pll_locked = CSRStatus()
self.clock_domains.cd_rtio = ClockDomain()
self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
rtio_external_clk = Signal()
clk_synth_se = Signal()
clk_synth = platform.request("si5324_clkout_fabric")
platform.add_period_constraint(clk_synth.p, 8.0)
self.specials += [
Instance("IBUFGDS",
p_DIFF_TERM="TRUE",
p_IBUF_LOW_PWR="TRUE",
i_I=clk_synth.p,
i_IB=clk_synth.n,
o_O=clk_synth_se),
Instance("BUFG", i_I=clk_synth_se, o_O=rtio_external_clk),
]
platform.add_false_path_constraints(rtio_external_clk,
rtio_internal_clk)
pll_locked = Signal()
rtio_clk = Signal()
rtiox4_clk = Signal()
ext_clkout_clk = Signal()
self.specials += [
Instance(
"PLLE2_ADV",
p_STARTUP_WAIT="FALSE",
o_LOCKED=pll_locked,
p_REF_JITTER1=0.01,
p_CLKIN1_PERIOD=8.0,
p_CLKIN2_PERIOD=8.0,
i_CLKIN1=rtio_internal_clk,
i_CLKIN2=rtio_external_clk,
# Warning: CLKINSEL=0 means CLKIN2 is selected
i_CLKINSEL=~self._clock_sel.storage,
# VCO @ 1GHz when using 125MHz input
p_CLKFBOUT_MULT=8,
p_DIVCLK_DIVIDE=1,
i_CLKFBIN=self.cd_rtio.clk,
i_RST=self._pll_reset.storage,
o_CLKFBOUT=rtio_clk,
p_CLKOUT0_DIVIDE=2,
p_CLKOUT0_PHASE=0.0,
o_CLKOUT0=rtiox4_clk),
Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
MultiReg(pll_locked, self._pll_locked.status)
]
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_por = ClockDomain()
# TODO: replace with PLL
# Clocking
self.submodules.sys_clk = sys_osc = NXOSCA()
sys_osc.create_hf_clk(self.cd_sys, sys_clk_freq)
platform.add_period_constraint(self.cd_sys.clk, 1e9 / sys_clk_freq)
rst_n = platform.request("gsrn")
# Power On Reset
por_cycles = 4096
por_counter = Signal(log2_int(por_cycles), reset=por_cycles - 1)
self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
self.sync.por += If(por_counter != 0, por_counter.eq(por_counter - 1))
self.specials += AsyncResetSynchronizer(self.cd_por, ~rst_n)
self.specials += AsyncResetSynchronizer(self.cd_sys,
(por_counter != 0) | self.rst)
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
# # #
# Clk / Rst
clk27 = platform.request("clk27")
rst_n = platform.request("user_btn", 0)
self.comb += self.cd_sys.clk.eq(clk27)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n)
def __init__(self, clock_pads, pads):
self._reset = CSRStorage()
# # #
if hasattr(clock_pads, "phy"):
self.sync.base50 += clock_pads.phy.eq(~clock_pads.phy)
self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain()
self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx)
self.comb += self.cd_eth_tx.clk.eq(clock_pads.tx)
reset = self._reset.storage
if hasattr(pads, "rst_n"):
self.comb += pads.rst_n.eq(~reset)
self.specials += [
AsyncResetSynchronizer(self.cd_eth_tx, reset),
AsyncResetSynchronizer(self.cd_eth_rx, reset),
]
def __init__(self, width, depth, idomain, odomain):
self.din = Signal(width)
self.dout = Signal(width)
# # #
reset = Signal()
cd_write = ClockDomain()
cd_read = ClockDomain()
self.comb += [
cd_write.clk.eq(ClockSignal(idomain)),
cd_read.clk.eq(ClockSignal(odomain)),
reset.eq(ResetSignal(idomain) | ResetSignal(odomain))
]
self.specials += [
AsyncResetSynchronizer(cd_write, reset),
AsyncResetSynchronizer(cd_read, reset)
]
self.clock_domains += cd_write, cd_read
wrpointer = Signal(max=depth, reset=depth//2)
rdpointer = Signal(max=depth)
storage = Memory(width, depth)
self.specials += storage
wrport = storage.get_port(write_capable=True, clock_domain="write")
rdport = storage.get_port(clock_domain="read")
self.specials += wrport, rdport
self.sync.write += wrpointer.eq(wrpointer + 1)
self.sync.read += rdpointer.eq(rdpointer + 1)
self.comb += [
wrport.we.eq(1),
wrport.adr.eq(wrpointer),
wrport.dat_w.eq(self.din),
rdport.adr.eq(rdpointer),
self.dout.eq(rdport.dat_r)
]
def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_clk200 = ClockDomain()
clk50 = platform.request("clk50")
self.reset = Signal()
pll_locked = Signal()
pll_fb = Signal()
pll_sys = Signal()
pll_clk200 = Signal()
self.specials += [
Instance("PLLE2_BASE",
p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
# VCO @ 1GHz
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=20.0,
p_CLKFBOUT_MULT=20, p_DIVCLK_DIVIDE=1,
i_CLKIN1=clk50, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
# 125MHz
p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
# 200MHz
p_CLKOUT3_DIVIDE=5, p_CLKOUT3_PHASE=0.0, o_CLKOUT3=pll_clk200
),
Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll_locked | self.reset),
AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | self.reset)
]
reset_counter = Signal(4, reset=15)
ic_reset = Signal(reset=1)
self.sync.clk200 += \
If(reset_counter != 0,
reset_counter.eq(reset_counter - 1)
).Else(
ic_reset.eq(0)
)
self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
def __init__(self, clk, rst):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_clk125 = ClockDomain()
# # #
self.comb += self.cd_sys.clk.eq(clk)
self.specials += AsyncResetSynchronizer(self.cd_sys, rst)
self.submodules.pll = pll = S7PLL()
pll.register_clkin(clk, 100e6)
pll.create_clkout(self.cd_clk125, 125e6)
def __init__(self, clock_pads, pads):
self._reset = CSRStorage()
# # #
self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain()
self.specials += [
Instance("BUFG", i_I=clock_pads.rx, o_O=self.cd_eth_rx.clk),
DDROutput(1, 0, clock_pads.tx, ClockSignal("eth_tx"))
]
self.comb += self.cd_eth_tx.clk.eq(self.cd_eth_rx.clk)
reset = self._reset.storage
if hasattr(pads, "rst_n"):
self.comb += pads.rst_n.eq(~reset)
self.specials += [
AsyncResetSynchronizer(self.cd_eth_tx, reset),
AsyncResetSynchronizer(self.cd_eth_rx, reset),
]
def __init__(self, platform, sys_clk_freq):
self.rst = CSR() # not used
# # #
clk = platform.request("clk")
rst = platform.request("rst")
platform.add_period_constraint(clk, 1e9 / sys_clk_freq)
self.clock_domains.cd_sys = ClockDomain()
self.comb += self.cd_sys.clk.eq(clk)
self.specials += AsyncResetSynchronizer(self.cd_sys, rst)
def create_clkout(self, cd, freq, phase=0, margin=1e-2, with_reset=True):
(clko_freq_min, clko_freq_max) = self.clko_freq_range
assert freq >= clko_freq_min
assert freq <= clko_freq_max
assert self.nclkouts < self.nclkouts_max
clkout = Signal()
self.clkouts[self.nclkouts] = (clkout, freq, phase, margin)
if with_reset:
self.specials += AsyncResetSynchronizer(cd, ~self.locked)
self.comb += cd.clk.eq(clkout)
create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts)
self.nclkouts += 1
def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0):
self._reset = CSRStorage()
# # #
self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain()
# RX : Let the synthesis tool insert the appropriate clock buffer
self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx)
# TX : GMII: Drive clock_pads.gtx, clock_pads.tx unused
# MII: Use PHY clock_pads.tx as eth_tx_clk, do not drive clock_pads.gtx
self.specials += DDROutput(1, mii_mode, clock_pads.gtx, ClockSignal("eth_tx"))
if isinstance(mii_mode, int) and (mii_mode == 0):
self.specials += Instance("BUFG",
i_I = self.cd_eth_rx.clk,
o_O = self.cd_eth_tx.clk,
)
else:
# XXX Xilinx specific, replace BUFGMUX with a generic clock buffer?
self.specials += Instance("BUFGMUX",
i_I0 = self.cd_eth_rx.clk,
i_I1 = clock_pads.tx,
i_S = mii_mode,
o_O = self.cd_eth_tx.clk,
)
reset = Signal()
if with_hw_init_reset:
self.submodules.hw_reset = LiteEthPHYHWReset()
self.comb += reset.eq(self._reset.storage | self.hw_reset.reset)
else:
self.comb += reset.eq(self._reset.storage)
self.comb += pads.rst_n.eq(~reset)
self.specials += [
AsyncResetSynchronizer(self.cd_eth_tx, reset),
AsyncResetSynchronizer(self.cd_eth_rx, reset),
]
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys_pll = ClockDomain()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
self.clock_domains.cd_idelay = ClockDomain()
self.clock_domains.cd_uart = ClockDomain()
self.clock_domains.cd_eth = ClockDomain()
# # #
self.submodules.main_pll = main_pll = USMMCM(speedgrade=-2)
self.comb += main_pll.reset.eq(platform.request("cpu_reset"))
main_pll.register_clkin(platform.request("clk125"), 125e6)
main_pll.create_clkout(self.cd_sys_pll, sys_clk_freq)
main_pll.create_clkout(self.cd_idelay, 200e6, with_reset=False)
main_pll.create_clkout(self.cd_uart, 100e6)
main_pll.create_clkout(self.cd_eth, 200e6)
main_pll.expose_drp()
self.submodules.pll = pll = USMMCM(speedgrade=-2)
self.comb += pll.reset.eq(~main_pll.locked)
pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq)
pll.create_clkout(self.cd_pll4x,
sys_clk_freq * 4,
buf=None,
with_reset=False)
self.specials += [
Instance(
"BUFGCE_DIV",
p_BUFGCE_DIVIDE=4,
i_CE=1,
i_I=self.cd_pll4x.clk,
o_O=self.cd_sys.clk,
),
Instance(
"BUFGCE",
i_CE=1,
i_I=self.cd_pll4x.clk,
o_O=self.cd_sys4x.clk,
),
AsyncResetSynchronizer(self.cd_idelay, ~pll.locked),
]
self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay,
cd_sys=self.cd_sys)
sys_clk_counter = Signal(32)
self.sync += sys_clk_counter.eq(sys_clk_counter + 1)
self.sys_clk_counter = CSRStatus(32)
self.comb += self.sys_clk_counter.status.eq(sys_clk_counter)
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
# # #
self.stop = Signal()
self.reset = Signal()
# Clk / Rst
clk12 = platform.request("clk12")
rst = platform.request("user_btn", 0)
# Power on reset
por_count = Signal(16, reset=2**16 - 1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(clk12)
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# PLL
sys2x_clk_ecsout = Signal()
self.submodules.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(~por_done | rst | self.rst)
pll.register_clkin(clk12, 12e6)
pll.create_clkout(self.cd_sys2x_i, 2 * sys_clk_freq)
pll.create_clkout(self.cd_init, 25e6)
self.specials += [
Instance(
"ECLKBRIDGECS",
i_CLK0=self.cd_sys2x_i.clk,
i_SEL=0,
o_ECSOUT=sys2x_clk_ecsout,
),
Instance("ECLKSYNCB",
i_ECLKI=sys2x_clk_ecsout,
i_STOP=self.stop,
o_ECLKO=self.cd_sys2x.clk),
Instance("CLKDIVF",
p_DIV="2.0",
i_ALIGNWD=0,
i_CLKI=self.cd_sys2x.clk,
i_RST=self.reset,
o_CDIVX=self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
]
self.comb += platform.request("dram_vtt_en").eq(1)
def __init__(self, platform, sys_clk_freq):
assert sys_clk_freq == 12e6
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_usb_12 = ClockDomain()
self.clock_domains.cd_usb_48 = ClockDomain()
# # #
# Clk/Rst
clk48 = platform.request("clk48")
platform.add_period_constraint(clk48, 1e9 / 48e6)
# Power On Reset
por_count = Signal(16, reset=2**16 - 1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(ClockSignal())
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# USB PLL
self.submodules.pll = pll = iCE40PLL()
#self.comb += pll.reset.eq(self.rst) # FIXME: Add proper iCE40PLL reset support and add back | self.rst.
pll.clko_freq_range = (
12e6, 275e9
) # FIXME: improve iCE40PLL to avoid lowering clko_freq_min.
pll.register_clkin(clk48, 48e6)
pll.create_clkout(self.cd_usb_12, 12e6, with_reset=False)
self.comb += self.cd_usb_48.clk.eq(clk48)
self.specials += AsyncResetSynchronizer(self.cd_usb_12,
~por_done | ~pll.locked)
self.specials += AsyncResetSynchronizer(self.cd_usb_48,
~por_done | ~pll.locked)
# Sys Clk
self.comb += self.cd_sys.clk.eq(self.cd_usb_12.clk)
self.specials += AsyncResetSynchronizer(self.cd_sys,
~por_done | ~pll.locked)
def __init__(self, platform, core_config):
assert core_config["memtype"] in ["DDR4"]
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain()
self.clock_domains.cd_sys4x_pll = ClockDomain()
self.clock_domains.cd_iodelay = ClockDomain()
# # #
clk = platform.request("clk")
rst = platform.request("rst")
# Power On Reset
por_count = Signal(32, reset=int(core_config["input_clk_freq"]*100/1e3)) # 100ms
por_done = Signal()
self.comb += self.cd_por.clk.eq(clk)
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# Sys PLL
self.submodules.sys_pll = sys_pll = USMMCM(speedgrade=core_config["speedgrade"])
self.comb += sys_pll.reset.eq(rst)
sys_pll.register_clkin(clk, core_config["input_clk_freq"])
sys_pll.create_clkout(self.cd_iodelay, core_config["iodelay_clk_freq"])
sys_pll.create_clkout(self.cd_sys4x_pll, 4*core_config["sys_clk_freq"], buf=None)
self.comb += platform.request("pll_locked").eq(sys_pll.locked)
self.specials += [
Instance("BUFGCE_DIV", name="main_bufgce_div",
p_BUFGCE_DIVIDE=4,
i_CE=por_done, i_I=self.cd_sys4x_pll.clk, o_O=self.cd_sys.clk),
Instance("BUFGCE", name="main_bufgce",
i_CE=por_done, i_I=self.cd_sys4x_pll.clk, o_O=self.cd_sys4x.clk),
AsyncResetSynchronizer(self.cd_sys4x, ~por_done | ~sys_pll.locked | rst),
AsyncResetSynchronizer(self.cd_sys, ~por_done | ~sys_pll.locked | rst),
]
# IODelay Ctrl
self.submodules.idelayctrl = USIDELAYCTRL(self.cd_iodelay, cd_sys=self.cd_sys)
def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain()
clk = platform.request("clk_in")
platform.add_period_constraint(clk, 1e9/30e6)
# pll
self.submodules.pll = pll = ECP5PLL()
pll.register_clkin(clk, 30e6)
pll.create_clkout(self.cd_sys, 60e6)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked)
def __init__(self, platform, clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain()
self.clock_domains.cd_base50 = ClockDomain()
f0 = 32*1000000
clk32 = platform.request("clk32")
clk32a = Signal()
self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a)
clk32b = Signal()
self.specials += Instance("BUFIO2", p_DIVIDE=1,
p_DIVIDE_BYPASS="******", p_I_INVERT="FALSE",
i_I=clk32a, o_DIVCLK=clk32b)
f = Fraction(int(clk_freq), int(f0))
n, m, p = f.denominator, f.numerator, 8
assert f0/n*m == clk_freq
pll_lckd = Signal()
pll_fb = Signal()
pll = Signal(6)
self.specials.pll = Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6",
p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1,
p_CLKIN1_PERIOD=1000000000/f0, p_CLKIN2_PERIOD=0.,
i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5,
o_CLKOUT3=pll[3], p_CLKOUT3_DUTY_CYCLE=.5,
o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5,
o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5,
p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//1,
p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//1,
p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=p//1,
p_CLKOUT3_PHASE=0., p_CLKOUT3_DIVIDE=p//1,
p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1, # sys
p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1, # sys_ps
)
self.specials += Instance("BUFG", i_I=pll[4], o_O=self.cd_sys.clk)
self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys_ps.clk)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd)
self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
p_INIT=0, p_SRTYPE="SYNC",
i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,
o_Q=platform.request("sdram_clock"))
self.specials += Instance("BUFG", i_I=platform.request("clk50"), o_O=self.cd_base50.clk)
def __init__(self, clock_pads, pads, with_hw_init_reset, tx_delay=2e-9):
self._reset = CSRStorage()
# # #
# RX Clock
self.clock_domains.cd_eth_rx = ClockDomain()
self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx)
# TX Clock
self.clock_domains.cd_eth_tx = ClockDomain()
self.comb += self.cd_eth_tx.clk.eq(self.cd_eth_rx.clk)
tx_delay_taps = int(tx_delay / 25e-12) # 25ps per tap
assert tx_delay_taps < 128
eth_tx_clk_o = Signal()
self.specials += [
DDROutput(clk=ClockSignal("eth_tx"), i1=1, i2=0, o=eth_tx_clk_o),
Instance("DELAYG",
p_DEL_MODE="SCLK_ALIGNED",
p_DEL_VALUE=tx_delay_taps,
i_A=eth_tx_clk_o,
o_Z=clock_pads.tx)
]
# Reset
self.reset = reset = Signal()
if with_hw_init_reset:
self.submodules.hw_reset = LiteEthPHYHWReset()
self.comb += reset.eq(self._reset.storage | self.hw_reset.reset)
else:
self.comb += reset.eq(self._reset.storage)
if hasattr(pads, "rst_n"):
self.comb += pads.rst_n.eq(~reset)
self.specials += [
AsyncResetSynchronizer(self.cd_eth_tx, reset),
AsyncResetSynchronizer(self.cd_eth_rx, reset),
]
def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0):
self._reset = CSRStorage()
# # #
self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain()
self.comb += self.cd_eth_tx.clk.eq(ClockSignal("eth_tx_sclk"))
#self.clock_domains.cd_eth_rx = ClockDomain()
#self.clock_domains.cd_eth_tx = ClockDomain()
# RX : Let the synthesis tool insert the appropriate clock buffer
self.comb += self.cd_eth_rx.clk.eq(ClockSignal("eth_rx_sclk"))
# TX : GMII: Drive clock_pads.gtx, clock_pads.tx unused
# MII: Use PHY clock_pads.tx as eth_tx_clk, do not drive clock_pads.gtx
#self.specials += DDROutput(1, 0, clock_pads.tx, ClockSignal("eth_tx"))
# hack to pass signal through the PLL to bring it from GR to Clock routing
#self.comb += self.cd_eth_tx.clk.eq(ClockSignal("clk125"))
#eth_rx_clk_ibuf = Signal()
#self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx)
# Reset
reset = Signal()
if with_hw_init_reset:
self.submodules.hw_reset = LiteEthPHYHWReset()
self.comb += reset.eq(self._reset.storage | self.hw_reset.reset)
else:
self.comb += reset.eq(self._reset.storage)
if hasattr(pads, "rst_n"):
self.comb += pads.rst_n.eq(~reset)
self.specials += [
AsyncResetSynchronizer(self.cd_eth_tx, reset),
AsyncResetSynchronizer(self.cd_eth_rx, reset),
]
def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
self.clock_domains.cd_clk10 = ClockDomain(
) # FIXME: for initial LiteSDCard tests.
# # #
# Clk / Rst
clk25 = platform.request("clk25")
rst = platform.request("rst")
# PLL
self.submodules.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(rst)
pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk10, 10e6)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst)
self.specials += AsyncResetSynchronizer(self.cd_clk10,
~pll.locked | rst)
# USB PLL
if with_usb_pll:
self.submodules.usb_pll = usb_pll = ECP5PLL()
usb_pll.register_clkin(clk25, 25e6)
self.clock_domains.cd_usb_12 = ClockDomain()
self.clock_domains.cd_usb_48 = ClockDomain()
usb_pll.create_clkout(self.cd_usb_12, 12e6, margin=0)
usb_pll.create_clkout(self.cd_usb_48, 48e6, margin=0)
# SDRAM clock
self.specials += DDROutput(1, 0, platform.request("sdram_clock"),
ClockSignal("sys_ps"))
# Prevent ESP32 from resetting FPGA
self.comb += platform.request("wifi_gpio0").eq(1)
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_por = ClockDomain()
self.clock_domains.cd_sys = ClockDomain()
# Built in OSC
self.submodules.hf_clk = NXOSCA()
hf_clk_freq = 25e6
self.hf_clk.create_hf_clk(self.cd_por, hf_clk_freq)
# Power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
self.rst_n = platform.request("gsrn")
self.specials += AsyncResetSynchronizer(self.cd_por, ~self.rst_n)
# PLL
self.submodules.sys_pll = sys_pll = NXPLL(platform=platform, create_output_port_clocks=True)
sys_pll.register_clkin(self.cd_por.clk, hf_clk_freq)
sys_pll.create_clkout(self.cd_sys, sys_clk_freq)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~self.sys_pll.locked | ~por_done )
def __init__(self, platform, use_rtio_clock=False):
self.ibuf_disable = CSRStorage(reset=1)
self.jreset = CSRStorage(reset=1)
self.jref = Signal()
self.refclk = Signal()
self.clock_domains.cd_jesd = ClockDomain()
refclk2 = Signal()
refclk_pads = platform.request("dac_refclk", 0)
platform.add_period_constraint(refclk_pads.p, 1e9 / self.refclk_freq)
self.specials += [
Instance("IBUFDS_GTE3",
i_CEB=self.ibuf_disable.storage,
p_REFCLK_HROW_CK_SEL=0b00,
i_I=refclk_pads.p,
i_IB=refclk_pads.n,
o_O=self.refclk,
o_ODIV2=refclk2),
AsyncResetSynchronizer(self.cd_jesd, self.jreset.storage),
]
if use_rtio_clock:
self.cd_jesd.clk.attr.add("keep")
self.comb += self.cd_jesd.clk.eq(ClockSignal("rtio"))
else:
self.specials += Instance("BUFG_GT",
i_I=refclk2,
o_O=self.cd_jesd.clk)
jref = platform.request("dac_sysref")
jref_se = Signal()
jref_r = Signal()
self.specials += [
Instance("IBUFDS_IBUFDISABLE",
p_USE_IBUFDISABLE="TRUE",
p_SIM_DEVICE="ULTRASCALE",
i_IBUFDISABLE=self.ibuf_disable.storage,
i_I=jref.p,
i_IB=jref.n,
o_O=jref_se),
# SYSREF normally meets s/h at the FPGA, except during margin
# scan and before full initialization.
# Be paranoid and use a double-register anyway.
Instance("FD",
i_C=ClockSignal("jesd"),
i_D=jref_se,
o_Q=jref_r,
attr={("IOB", "TRUE")}),
Instance("FD", i_C=ClockSignal("jesd"), i_D=jref_r, o_Q=self.jref)
]
def __init__(self,
platform,
sys_clk_freq,
with_usb_pll=False,
with_rst=True,
sdram_rate="1:1"):
self.clock_domains.cd_sys = ClockDomain()
if sdram_rate == "1:2":
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
else:
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
# # #
# Clk / Rst
clk25 = platform.request("clk25")
rst_n = 1 if not with_rst else platform.request("user_btn_n", 0)
# PLL
self.submodules.pll = pll = ECP5PLL()
pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
if sdram_rate == "1:2":
pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq)
pll.create_clkout(
self.cd_sys2x_ps, 2 * sys_clk_freq,
phase=180) # Idealy 90° but needs to be increased.
else:
pll.create_clkout(
self.cd_sys_ps, sys_clk_freq,
phase=180) # Idealy 90° but needs to be increased.
self.specials += AsyncResetSynchronizer(self.cd_sys,
~pll.locked | ~rst_n)
# USB PLL
if with_usb_pll:
self.submodules.usb_pll = usb_pll = ECP5PLL()
usb_pll.register_clkin(clk25, 25e6)
self.clock_domains.cd_usb_12 = ClockDomain()
self.clock_domains.cd_usb_48 = ClockDomain()
usb_pll.create_clkout(self.cd_usb_12, 12e6, margin=0)
usb_pll.create_clkout(self.cd_usb_48, 48e6, margin=0)
# SDRAM clock
sdram_clk = ClockSignal("sys2x_ps" if sdram_rate ==
"1:2" else "sys_ps")
self.specials += DDROutput(1, 0, platform.request("sdram_clock"),
sdram_clk)
def __init__(self, clock_pads, pads, refclk_cd, with_hw_init_reset):
self._reset = CSRStorage()
# # #
# RX/TX clocks
self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain()
# When no refclk_cd, use clock_pads.ref_clk as RMII reference clock.
if refclk_cd is None:
self.comb += self.cd_eth_rx.clk.eq(clock_pads.ref_clk)
self.comb += self.cd_eth_tx.clk.eq(clock_pads.ref_clk)
# Else use refclk_cd as RMII reference clock (provided by user design).
else:
self.comb += self.cd_eth_rx.clk.eq(ClockSignal(refclk_cd))
self.comb += self.cd_eth_tx.clk.eq(ClockSignal(refclk_cd))
# Drive clock_pads if provided.
if clock_pads is not None:
self.specials += DDROutput(0, 1, clock_pads.ref_clk,
ClockSignal("eth_tx"))
# Reset
self.reset = reset = Signal()
if with_hw_init_reset:
self.submodules.hw_reset = LiteEthPHYHWReset()
self.comb += reset.eq(self._reset.storage | self.hw_reset.reset)
else:
self.comb += reset.eq(self._reset.storage)
if hasattr(pads, "rst_n"):
self.comb += pads.rst_n.eq(~reset)
self.specials += [
AsyncResetSynchronizer(self.cd_eth_tx, reset),
AsyncResetSynchronizer(self.cd_eth_rx, reset),
]
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
# # #
self.stop = Signal()
self.reset = Signal()
# Clk / Rst
clk100 = platform.request("clk100")
rst_n = platform.request("rst_n")
# Power on reset
por_count = Signal(16, reset=2**16 - 1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(clk100)
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# PLL
self.submodules.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(~por_done | ~rst_n | self.rst)
pll.register_clkin(clk100, 100e6)
pll.create_clkout(self.cd_sys2x_i, 2 * sys_clk_freq)
pll.create_clkout(self.cd_init, 25e6)
self.specials += [
Instance("ECLKSYNCB",
i_ECLKI=self.cd_sys2x_i.clk,
i_STOP=self.stop,
o_ECLKO=self.cd_sys2x.clk),
Instance("CLKDIVF",
p_DIV="2.0",
i_ALIGNWD=0,
i_CLKI=self.cd_sys2x.clk,
i_RST=self.reset,
o_CDIVX=self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
]
# HDMI
self.clock_domains.cd_hdmi = ClockDomain(reset_less=True)
#pll.create_clkout(self.cd_hdmi, 148.5e6) # for terminal "1920x1080@60Hz"
#pll.create_clkout(self.cd_hdmi, 160e6) # for terminal "1920x1080@60Hz"
#pll.create_clkout(self.cd_hdmi, 80e6) # for terminal "1920x1080@30Hz"
pll.create_clkout(self.cd_hdmi, 40e6) # for terminal "800x600@60Hz"
def __init__(self,
platform,
sys_clk_freq,
with_usb_pll=False,
sdram_rate="1:1"):
self.clock_domains.cd_sys = ClockDomain()
if sdram_rate == "1:2":
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
else:
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
# # #
# Clk / Rst
clk25 = platform.request("clk25")
rst = platform.request("rst")
# PLL
self.submodules.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(rst)
pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
if sdram_rate == "1:2":
pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq)
pll.create_clkout(
self.cd_sys2x_ps, 2 * sys_clk_freq,
phase=180) # Idealy 90° but needs to be increased.
else:
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst)
# USB PLL
if with_usb_pll:
self.submodules.usb_pll = usb_pll = ECP5PLL()
usb_pll.register_clkin(clk25, 25e6)
self.clock_domains.cd_usb_12 = ClockDomain()
self.clock_domains.cd_usb_48 = ClockDomain()
usb_pll.create_clkout(self.cd_usb_12, 12e6, margin=0)
usb_pll.create_clkout(self.cd_usb_48, 48e6, margin=0)
# SDRAM clock
sdram_clk = ClockSignal("sys2x_ps" if sdram_rate ==
"1:2" else "sys_ps")
self.specials += DDROutput(1, 0, platform.request("sdram_clock"),
sdram_clk)
# Prevent ESP32 from resetting FPGA
self.comb += platform.request("wifi_gpio0").eq(1)
