def test_incr():
bus = axi.Interface()
dut = Incr(bus.aw)
def _test_fixed():
yield from bus.write_aw(0, 0xff100, 16 - 1, burst_size(4), Burst.fixed)
assert (yield dut.addr) == 0xff100
def _test_incr():
yield from bus.write_aw(0, 0xff101, 16 - 1, burst_size(4), Burst.incr)
assert (yield dut.addr) == 0xff104
def _test_wrap():
yield from bus.write_aw(0, 0xff100, 16 - 1, burst_size(4), Burst.wrap)
assert (yield dut.addr) == 0xff104
wrap_boundary = int(0xff100 / (16 * 4)) * 16 * 4
yield from bus.write_aw(0, wrap_boundary + 14 * 4, 16 - 1,
burst_size(4), Burst.wrap)
assert (yield dut.addr) == wrap_boundary + 15 * 4
yield from bus.write_aw(0, wrap_boundary + 15 * 4, 16 - 1,
burst_size(4), Burst.wrap)
assert (yield dut.addr) == wrap_boundary
def testbench_incr():
yield bus.aw.ready.eq(1)
yield from _test_fixed()
yield from _test_incr()
yield from _test_wrap()
run_simulation(dut,
testbench_incr(),
vcd_name=file_tmp_folder("test_incr.vcd"))
def test_upscaler():
i = axi.Interface()
dw = i.data_width
dut = stream.Converter(8, dw)
source, sink = dut.source, dut.sink
write = partial(write_data, sink)
read = partial(read_data, source)
def testbench_upscaler():
def push():
yield from write(0x11)
yield from write(0x22)
yield from write(0x33)
yield from write(0x44)
yield from write(0x55)
yield from write(0x66)
yield from write(0x77)
yield from write(0x88)
yield from write(0x99, eop=1)
def pull():
yield source.ack.eq(1)
assert (yield from read()) == 0x44332211
yield
assert (yield from read()) == 0x88776655
yield
assert (yield from read()) & 0xff == 0x99
return [
push(),
pull(),
]
run_simulation(dut, testbench_upscaler())
def test():
data = [1, 2, 0xa5, 3, 4, 0xa5, 0xa5, 5, 6, 0xa5, 0xa5, 0xa5, 7, 8,
0xa5, 0xa5, 0xa5, 0xa5, 9, 10]
aexpect = [1, 2, 4, 0xa5, 5, 6, 0xa5, 8, 0xa5, 0xa5, 9, 10]
bexpect = [3, 7]
dut = Unescaper(data_layout)
aout = []
bout = []
run_simulation(dut, _test_unescaper(dut, data, aout, bout),
vcd_name="escape.vcd")
assert aout == aexpect, (aout, aexpect)
assert bout == bexpect, (bout, bexpect)
def test_read_requester():
bus = dmac_bus.Interface()
dut = stream2axi._ReadRequester(bus)
def testbench_read_requester():
assert (yield bus.da.ready) == 1
yield bus.dr.ready.eq(1)
assert (yield bus.da.valid) == 0
yield dut.burst_request.eq(1)
yield
for _ in range(2):
assert (yield bus.dr.valid) == 1
assert (yield bus.dr.type) == dmac_bus.Type.burst
for __ in range(16):
yield
assert (yield bus.dr.valid) == 0
yield from bus.write_da(dmac_bus.Type.burst)
yield
# single transfers
assert (yield bus.dr.valid) == 1
assert (yield bus.dr.type) == dmac_bus.Type.burst
for _ in range(16):
yield from bus.write_da(dmac_bus.Type.single)
yield
# still in read mode?
assert (yield bus.dr.valid) == 0
# flush request
yield from bus.write_da(dmac_bus.Type.flush)
yield
yield dut.burst_request.eq(0)
# flush ack
assert (yield bus.dr.valid) == 1
assert (yield bus.dr.type) == dmac_bus.Type.flush
yield
assert (yield bus.dr.valid) == 0
# flush request when idle
yield from bus.write_da(dmac_bus.Type.flush)
yield
# flush ack
assert (yield bus.dr.valid) == 1
assert (yield bus.dr.type) == dmac_bus.Type.flush
yield
assert (yield bus.dr.valid) == 0
run_simulation(dut,
testbench_read_requester(),
vcd_name=file_tmp_folder("test_read_requester.vcd"))
def test():
data = [
1, 2, 0xa5, 3, 4, 0xa5, 0xa5, 5, 6, 0xa5, 0xa5, 0xa5, 7, 8, 0xa5, 0xa5,
0xa5, 0xa5, 9, 10
]
aexpect = [1, 2, 4, 0xa5, 5, 6, 0xa5, 8, 0xa5, 0xa5, 9, 10]
bexpect = [3, 7]
dut = Unescaper(data_layout)
aout = []
bout = []
run_simulation(dut,
_test_unescaper(dut, data, aout, bout),
vcd_name="escape.vcd")
assert aout == aexpect, (aout, aexpect)
assert bout == bexpect, (bout, bexpect)
def test_downscaler():
i = axi.Interface()
dw = i.data_width
dut = stream.Converter(dw, 8)
source, sink = dut.source, dut.sink
write = partial(write_data, sink)
read = partial(read_data, source)
def testbench_downscaler():
def push():
yield from write(0x44332211)
yield from write(0x88776655, eop=True)
def pull():
yield source.ack.eq(1)
assert (yield from read()) == 0x11
yield
assert (yield from read()) == 0x22
yield
assert (yield from read()) == 0x33
yield
assert (yield from read()) == 0x44
yield
assert (yield from read()) == 0x55
yield
assert (yield from read()) == 0x66
yield
assert (yield from read()) == 0x77
yield
assert (yield from read()) == 0x88
assert (yield source.eop) == 1
return [
push(),
pull(),
]
run_simulation(dut,
testbench_downscaler(),
vcd_name=file_tmp_folder("test_downscaler.vcd"))
def test_reader():
i = axi.Interface()
dw = i.data_width
dut = Reader(i)
dut.submodules.downscaler = stream.Converter(dw, 8)
dut.comb += dut.source.connect(dut.downscaler.sink)
source, sink = dut.downscaler.source, dut.sink
request = partial(request_addr, sink)
read = partial(read_data, source)
def testbench_reader():
def push_addr():
yield from request(0x11223344, eop=True)
def pull_data():
yield source.ack.eq(1)
assert (yield from read()) == 0x04
yield
assert (yield from read()) == 0x03
yield
assert (yield from read()) == 0x02
yield
assert (yield from read()) == 0x01
assert (yield source.eop) == 1
def ar_and_r_channel():
assert (yield from i.read_ar()).addr == 0x11223344
yield from i.write_r(0x55, 0x01020304, last=1)
return [
push_addr(),
pull_data(),
ar_and_r_channel(),
]
run_simulation(dut,
testbench_reader(),
vcd_name=file_tmp_folder("test_reader.vcd"))
def test_countdown():
dut = axi_dma.Countdown(4)
def testbench_countdown():
assert (yield dut.done) == 1
yield dut.we.eq(1)
yield dut.count_w.eq(4)
yield
yield dut.we.eq(0)
yield
assert (yield dut.done) == 0
yield dut.ce.eq(1)
yield
yield
yield
yield
yield
assert (yield dut.done) == 1
yield dut.ce.eq(0)
yield
run_simulation(dut,
testbench_countdown(),
vcd_name=file_tmp_folder("test_countdown.vcd"))
def test_cmdproc(self):
write_transactions = []
def collector():
yield "passive"
while 1:
if (yield self.tb.cm.master.we):
write_transactions.append(((yield self.tb.cm.master.adr), (yield self.tb.cm.master.dat_w)))
yield
def do_outbound_fifo_rd(o):
yield o.writable.eq(1)
while (yield o.we) == 0:
yield
v = yield o.din
yield o.writable.eq(0)
return v
def do_income_fifo_wr(o, v):
yield o.readable.eq(1)
yield o.dout.eq(v)
while (yield o.re) == 0:
yield
yield
yield o.readable.eq(0)
def gen():
for i in range(5):
yield
yield from do_income_fifo_wr(self.tb.ff.incoming_fifo, 0x55)
yield from do_income_fifo_wr(self.tb.ff.incoming_fifo, 0x92)
yield from do_income_fifo_wr(self.tb.ff.incoming_fifo, 0x34)
yield from do_income_fifo_wr(self.tb.ff.incoming_fifo, 0x56)
yield from do_income_fifo_wr(self.tb.ff.incoming_fifo, 0xAA)
for i in range(10):
yield
self.assertEqual(write_transactions, [(0x1234, 0x56)])
self.sim = run_simulation(self.tb, [gen(), collector()], vcd_name="test_cmdproc.vcd")
def _sim_and_assert_testcase(self, testcase, testname, outdir):
"""Migen powered simulation and checking of a testcase.
Args:
testcase (TestDeclaration()): current test case.
testname (str): name of the current test.
outdir (str): output directory for the vcd file.
"""
def _make_dut(self):
if self._args is not None:
return self._dut_class(*self._args)
return self._dut_class()
def _set_input(dut, signame, in_value):
return getattr(dut, signame).eq(in_value)
def _get_output(dut, signame):
return (yield getattr(dut, signame))
def _unitbench_assert(signame, out_value, expected_value, testname,
tag, round_idx):
message = ("unitbench: `{}`; `{}`, round {}, " +
"test failed: `{}`: {}; expected {}").format(
testname, tag, round_idx, signame, out_value,
expected_value)
if expected_value is not None and out_value != expected_value:
raise UnitBenchAssertionError(out_value, expected_value,
message, round_idx)
def _sim(dut, testcase):
in_q, exp_q = testcase.get_io_queues()
round_idx = -1
ticks_idx = 0
while (not in_q.empty() or not exp_q.empty()):
in_values = None if in_q.empty() else in_q.get()
if in_values is not None:
# Set input signals to given values
for signame, in_value in in_values.items():
yield _set_input(dut, signame, in_value)
expected_values = None if exp_q.empty() else exp_q.get()
if expected_values is not None:
round_idx += 1
# Get output signals result and check errors in respect
# with espected values
for signame, expected_value in expected_values.items():
out_value = yield from _get_output(dut, signame)
_unitbench_assert(signame, out_value, expected_value,
testname, testcase.tag, round_idx)
yield
ticks_idx += 1
dut = self._dut_class(*self._args)
run_simulation(dut,
_sim(dut, testcase),
vcd_name=self._get_vcd_name(testname, testcase.tag,
outdir))
def test_writer():
i = axi.Interface()
dut = axi_dma.Writer(i, fifo_depth=4)
sink = dut.sink
def testbench_writer():
def tx():
yield sink.addr.eq(0x11223344)
yield sink.data.eq(0x11111111)
yield from write_ack(sink)
yield sink.data.eq(0x22222222)
yield from write_ack(sink)
yield sink.data.eq(0x33333333)
yield from write_ack(sink)
yield sink.data.eq(0x44444444)
yield from write_ack(sink)
# 2nd burst
yield sink.data.eq(0x11111111)
yield from write_ack(sink)
yield sink.data.eq(0x22222222)
yield from write_ack(sink)
yield sink.data.eq(0x33333333)
yield from write_ack(sink)
yield sink.data.eq(0x44444444)
yield from write_ack(sink)
yield sink.eop.eq(1)
yield from write_ack(sink)
yield sink.eop.eq(0)
# 3rd burst, partial, send only 8 bytes
yield sink.addr.eq(0x11223344)
yield sink.data.eq(0x11111100)
yield from write_ack(sink)
yield sink.data.eq(0x22222200)
yield from write_ack(sink)
yield sink.eop.eq(1)
yield from write_ack(sink)
yield sink.eop.eq(0)
def aw_channel():
assert attrgetter_aw((yield from
i.read_aw())) == (0x11223344, 3, Burst.incr)
# 2nd burst
assert attrgetter_aw((yield from
i.read_aw())) == (0x11223354, 3, Burst.incr)
# 3rd burst
assert attrgetter_aw((yield from
i.read_aw())) == (0x11223344, 3, Burst.incr)
def w_channel():
yield i.w.ready.eq(1)
assert attrgetter_w((yield from
i.read_w())) == (0x11111111, 0xf, 0)
assert attrgetter_w((yield from
i.read_w())) == (0x22222222, 0xf, 0)
assert attrgetter_w((yield from
i.read_w())) == (0x33333333, 0xf, 0)
assert attrgetter_w((yield from
i.read_w())) == (0x44444444, 0xf, 1)
# 2nd burst
assert attrgetter_w((yield from
i.read_w())) == (0x11111111, 0xf, 0)
assert attrgetter_w((yield from
i.read_w())) == (0x22222222, 0xf, 0)
assert attrgetter_w((yield from
i.read_w())) == (0x33333333, 0xf, 0)
assert attrgetter_w((yield from
i.read_w())) == (0x44444444, 0xf, 1)
# 3rd burst
assert attrgetter_w((yield from
i.read_w())) == (0x11111100, 0xf, 0)
assert attrgetter_w((yield from
i.read_w())) == (0x22222200, 0xf, 0)
assert attrgetter_w((yield from
i.read_w())) == (0x22222200, 0xf, 0)
assert attrgetter_w((yield from
i.read_w())) == (0x22222200, 0xf, 1)
yield i.w.ready.eq(0)
def b_channel():
yield from i.write_b(0)
yield from i.write_b(0)
yield from i.write_b(0)
return [tx(), aw_channel(), w_channel(), b_channel()]
run_simulation(dut,
testbench_writer(),
vcd_name=file_tmp_folder("test_writer.vcd"))
def test_transaction_arbiter():
mem_map = {
"s_0": 0x10000000,
"s_1": 0x20000000,
}
m_0 = axi.Interface()
m_1 = axi.Interface()
m = [m_0, m_1]
s_0 = axi.Interface()
s_1 = axi.Interface()
s = [(mem_decoder(mem_map["s_0"]), s_0),
(mem_decoder(mem_map["s_1"]), s_1)]
dut = axi.TransactionArbiter(m, s, npending=2)
def testbench_transaction_arbiter():
def request_m_0():
yield from m_0.write_ar(0x01, mem_map["s_0"], 0,
m_0.data_width // 8, Burst.fixed)
def response_s_0():
ar = s_0.ar
yield
yield
yield
yield ar.ready.eq(1)
yield
assert attrgetter_ar(
(yield from s_0.read_ar())) == (mem_map["s_0"], 0, Burst.fixed)
yield ar.ready.eq(0)
def transaction_s_0():
source = dut.r_transaction[0].source
yield from wait_stb(source)
assert (yield source.sel) == 1 << 0
yield from ack(source)
def request_m_1():
yield
yield from m_1.write_aw(0x02, mem_map["s_1"], 0,
m_0.data_width // 8, Burst.fixed)
def response_s_1():
aw = s_1.aw
yield
yield aw.ready.eq(1)
yield
assert attrgetter_aw(
(yield from s_1.read_aw())) == (mem_map["s_1"], 0, Burst.fixed)
yield aw.ready.eq(0)
def transaction_s_1():
source = dut.w_transaction[1].source
yield from wait_stb(source)
assert (yield source.sel) == 1 << 1
yield from ack(source)
return [
request_m_0(),
response_s_0(),
transaction_s_0(),
request_m_1(),
response_s_1(),
transaction_s_1(),
]
run_simulation(dut,
testbench_transaction_arbiter(),
vcd_name=file_tmp_folder("test_transaction_arbiter.vcd"))
from d_flip_flop import Dflipflop
from migen.sim import run_simulation
from migen.fhdl.structure import Signal
ff_D = Signal()
ff_Q = Signal()
ff_Qi = Signal()
ff = Dflipflop(ff_D, ff_Q, ff_Qi)
def testbench():
yield ff_D.eq(1)
yield
yield ff_D.eq(0)
yield
yield
yield ff_D.eq(1)
yield
yield
yield
yield ff_D.eq(0)
yield
yield
run_simulation(ff, testbench(), vcd_name="test_d_ff.vcd")
def test_reader():
i = axi.Interface()
dut = axi_dma.Reader(i, fifo_depth=4)
sink, source = dut.sink, dut.source
def testbench_reader():
def request_rx():
yield
# 1st burst
yield sink.addr.eq(0x11223344)
yield sink.n.eq(4)
yield sink.eop.eq(1)
yield from write_ack(sink)
yield sink.eop.eq(0)
# 2nd, 3rd burst
yield sink.addr.eq(0x11223350)
yield sink.n.eq(7)
yield from write_ack(sink)
def rx():
# 1st burst
yield source.ack.eq(1)
yield from wait_stb(source)
assert (yield source.data) == 0x11111111
assert (yield source.eop) == 0
yield
assert (yield source.data) == 0x22222222
assert (yield source.eop) == 0
yield
assert (yield source.data) == 0x33333333
assert (yield source.eop) == 0
yield
assert (yield source.data) == 0x44444444
assert (yield source.eop) == 1
yield
# 2nd burst
yield from wait_stb(source)
assert (yield source.data) == 0x11111100
assert (yield source.eop) == 0
yield
assert (yield source.data) == 0x22222200
assert (yield source.eop) == 0
yield
assert (yield source.data) == 0x33333300
assert (yield source.eop) == 0
yield
assert (yield source.data) == 0x44444400
assert (yield source.eop) == 0
yield
# 3rd burst
yield from wait_stb(source)
assert (yield source.data) == 0x11111101
assert (yield source.eop) == 0
yield
assert (yield source.data) == 0x22222202
assert (yield source.eop) == 0
yield
assert (yield source.data) == 0x33333303
assert (yield source.eop) == 1
yield
assert (yield source.stb) == 0
def ar_and_r_channel():
# 1st burst
assert attrgetter_ar((yield from
i.read_ar())) == (0x11223344, 3, Burst.incr)
yield from i.write_r(0x55, 0x11111111, okay, 0)
yield from i.write_r(0x55, 0x22222222, okay, 0)
yield from i.write_r(0x55, 0x33333333, okay, 0)
yield from i.write_r(0x55, 0x44444444, okay, 1)
# 2nd burst
assert attrgetter_ar((yield from
i.read_ar())) == (0x11223350, 3, Burst.incr)
yield from i.write_r(0x55, 0x11111100, okay, 0)
yield from i.write_r(0x55, 0x22222200, okay, 0)
yield from i.write_r(0x55, 0x33333300, okay, 0)
yield from i.write_r(0x55, 0x44444400, okay, 1)
# 3rd burst, subsequent
assert attrgetter_ar((yield from
i.read_ar())) == (0x11223360, 3, Burst.incr)
yield from i.write_r(0x55, 0x11111101, okay, 0)
yield from i.write_r(0x55, 0x22222202, okay, 0)
yield from i.write_r(0x55, 0x33333303, okay, 0)
yield from i.write_r(0x55, 0x44444404, okay, 1)
return [
request_rx(),
rx(),
ar_and_r_channel(),
]
run_simulation(dut,
testbench_reader(),
vcd_name=file_tmp_folder("test_reader.vcd"))
def test_axi2csr_mem(data_width):
dut = AXI2CSR(bus_csr=csr_bus.Interface(data_width=data_width))
# create memory through axi2csr
addr, size = dut.add_memory(0x20, read_only=False)
# create memory manually and add it later
mem2 = Memory(32, 8)
addr2, size2 = dut.add_memory(mem2, read_only=False)
# create memory and add ports manually
mem3 = Memory(32, 16)
# necessary otherwise will throw "Could not lower all specials"
dut.specials += mem3
mem3_port_write = mem3.get_port(write_capable=True)
mem3_port_read = mem3.get_port(write_capable=False)
addr3_write = dut.register_port(mem3_port_write, 0x40)
addr3_read = dut.register_port(mem3_port_read, 0x40)
write_aw = partial(dut.bus.write_aw,
size=burst_size(dut.bus.data_width // 8),
len_=0,
burst=Burst.fixed)
write_w = dut.bus.write_w
read_b = dut.bus.read_b
write_ar = partial(dut.bus.write_ar,
size=burst_size(dut.bus.data_width // 8),
len_=0,
burst=Burst.fixed)
read_r = dut.bus.read_r
def testbench_axi2csr_mem():
i = dut.bus
assert addr == 0x10000
assert addr2 == 0x10020
assert addr3_write == 0x10040
assert addr3_read == 0x10080
assert size == 0x20
assert size2 == 0x20
# mask is not necessary here as it should
# work as intended regardless of csr bus width
def aw_channel():
assert (yield i.aw.ready) == 1
yield from write_aw(0x01, addr + 0x00)
yield from write_aw(0x02, addr + 0x04)
yield from write_aw(0x03, addr2 + 0x08)
yield from write_aw(0x04, addr2 + 0x0c)
yield from write_aw(0x05, addr3_write + 0x00)
def w_channel():
yield from write_w(0, 0x11, strb=1)
yield from write_w(0, 0x11223344, strb=1)
yield from write_w(0, 0x33445566, strb=1)
yield from write_w(0, 0x778899AA, strb=1)
yield from write_w(0, 0xDEADBEEF)
def b_channel():
assert attrgetter_b((yield from read_b())) == (0x01, okay)
assert attrgetter_b((yield from read_b())) == (0x02, okay)
assert attrgetter_b((yield from read_b())) == (0x03, okay)
assert attrgetter_b((yield from read_b())) == (0x04, okay)
assert attrgetter_b((yield from read_b())) == (0x05, okay)
def ar_channel():
# cannot check if data written because internal_csr
# is created at the very end
yield from write_ar(0x11, addr + 0x00)
yield from write_ar(0x22, addr + 0x04)
yield from write_ar(0x33, addr2 + 0x08)
yield from write_ar(0x44, addr2 + 0x0c)
yield from write_ar(0x55, addr3_read + 0x00)
def r_channel():
# mem 1
assert attrgetter_r((yield from read_r())) == (0x11, 0x11, okay, 1)
assert attrgetter_r((yield from
read_r())) == (0x22, 0x11223344, okay, 1)
# mem 2
assert attrgetter_r((yield from
read_r())) == (0x33, 0x33445566, okay, 1)
assert attrgetter_r((yield from
read_r())) == (0x44, 0x778899AA, okay, 1)
# mem 3
assert attrgetter_r((yield from
read_r())) == (0x55, 0xDEADBEEF, okay, 1)
return [
aw_channel(),
w_channel(),
b_channel(),
r_channel(),
ar_channel(),
]
run_simulation(dut,
testbench_axi2csr_mem(),
vcd_name=file_tmp_folder("test_axi2csr_mem.vcd"))
def test_stream2axi_writer(): # noqa
bus = types.SimpleNamespace(axi=axi.Interface(), dmac=dmac_bus.Interface())
dut = stream2axi.Writer(bus.axi, bus.dmac)
write_aw = partial(bus.axi.write_aw,
size=burst_size(bus.axi.data_width // 8),
burst=Burst.fixed)
write_w = bus.axi.write_w
read_b = bus.axi.read_b
write_ar = partial(bus.axi.write_ar,
size=burst_size(bus.axi.data_width // 8),
burst=Burst.fixed)
read_r = bus.axi.read_r
def testbench_stream2axi_writer():
def source():
sink = dut.sink
yield sink.stb.eq(1)
for i in range(32):
while (yield sink.ack) == 0:
yield
yield sink.data.eq(i)
yield
def aw_channel():
assert (yield bus.axi.aw.ready) == 1
yield from write_aw(0x01, 0x00, len_=16 - 1)
def w_channel():
for _ in range(15):
yield from write_w(0, 0x11223344, last=0)
yield from write_w(0, 0x11223344, last=1)
def b_channel():
assert attrgetter_b((yield from read_b())) == (0x01, okay)
def ar_channel():
# wait for request
assert (yield from bus.dmac.read_dr()).type == dmac_bus.Type.burst
yield from write_ar(0x11, 0, len_=16 - 1)
# write ack
yield from bus.dmac.write_da(dmac_bus.Type.burst)
# wait for request
assert (yield from bus.dmac.read_dr()).type == dmac_bus.Type.burst
for i in range(10):
yield from write_ar(i, 0, len_=0)
# ack single tx
yield from bus.dmac.write_da(dmac_bus.Type.single)
# flush request
yield from bus.dmac.write_da(dmac_bus.Type.flush)
# wait for flush ack
assert (yield from bus.dmac.read_dr()).type == dmac_bus.Type.flush
def r_channel():
yield bus.axi.r.ready.eq(1)
for i in range(15):
assert attrgetter_r((yield from
read_r())) == (0x11, i, okay, 0)
assert attrgetter_r((yield from read_r())) == (0x11, 15, okay, 1)
for i in range(10):
assert attrgetter_r((yield from
read_r())) == (i, i + 16, okay, 1)
return [
source(),
aw_channel(),
w_channel(),
b_channel(),
ar_channel(),
r_channel(),
]
run_simulation(dut,
testbench_stream2axi_writer(),
vcd_name=file_tmp_folder("test_stream2axi_writer.vcd"))
def test_sram():
# most of the code was copied from CSR, as it also tests SRAM
# just with a different interface
dut = sram.SRAM(0x100, read_only=False, bus=axi.Interface())
write_aw = partial(dut.bus.write_aw,
size=burst_size(len(dut.bus.w.data) // 8),
len_=0,
burst=Burst.fixed)
write_w = dut.bus.write_w
read_b = dut.bus.read_b
write_ar = partial(dut.bus.write_ar,
size=burst_size(len(dut.bus.r.data) // 8),
len_=0,
burst=Burst.fixed)
read_r = dut.bus.read_r
# it's not csr but interface is identical
w_mon = partial(csr_w_mon, dut.port)
def testbench_sram():
i = dut.bus
def aw_channel():
assert (yield i.aw.ready) == 0
yield from write_aw(0x01, 0x00)
assert (yield i.aw.ready) == 1
yield from write_aw(0x02, 0x04)
yield from write_aw(0x03, 0x08)
yield from write_aw(0x04, 0x0c)
yield from write_aw(0x05, 0x40)
def w_channel():
yield from write_w(0, 0x11, strb=1)
yield from write_w(0, 0x22, strb=1)
yield from write_w(0, 0x33, strb=1)
yield from write_w(0, 0x44, strb=1)
yield from write_w(0, 0x11223344)
def b_channel():
assert attrgetter_b((yield from read_b())) == (0x01, okay)
assert attrgetter_b((yield from read_b())) == (0x02, okay)
assert attrgetter_b((yield from read_b())) == (0x03, okay)
assert attrgetter_b((yield from read_b())) == (0x04, okay)
assert attrgetter_b((yield from read_b())) == (0x05, okay)
def ar_channel():
# ensure data was actually written
assert attrgetter_csr_w_mon((yield from w_mon())) == (0x00, 0x11)
assert attrgetter_csr_w_mon((yield from w_mon())) == (0x01, 0x22)
assert attrgetter_csr_w_mon((yield from w_mon())) == (0x02, 0x33)
assert attrgetter_csr_w_mon((yield from w_mon())) == (0x03, 0x44)
# unlike csr, data width here can be only 32 bits, not 8/16
assert attrgetter_csr_w_mon((yield from
w_mon())) == (0x10, 0x11223344)
# ok, read it now
yield from write_ar(0x11, 0x00)
yield from write_ar(0x22, 0x04)
yield from write_ar(0x33, 0x08)
yield from write_ar(0x44, 0x0c)
yield from write_ar(0x55, 0x40)
def r_channel():
assert attrgetter_r((yield from read_r())) == (0x11, 0x11, okay, 1)
assert attrgetter_r((yield from read_r())) == (0x22, 0x22, okay, 1)
assert attrgetter_r((yield from read_r())) == (0x33, 0x33, okay, 1)
assert attrgetter_r((yield from read_r())) == (0x44, 0x44, okay, 1)
assert attrgetter_r((yield from
read_r())) == (0x55, 0x11223344, okay, 1)
return [
aw_channel(),
w_channel(),
b_channel(),
r_channel(),
ar_channel(),
]
run_simulation(dut,
testbench_sram(),
vcd_name=file_tmp_folder("test_sram.vcd"))
from migen.sim import run_simulation
from fomu_soc import Fomu
from fomu_platform import FomuPlatform
platform = FomuPlatform(revision="pvt")
fomu = Fomu(platform)
def testbench():
yield fomu.cd_sys.clk
yield fomu.cd_sys.rst
yield fomu.address_bus
yield
run_simulation(fomu, testbench())
def test():
# print(verilog.convert(TB()))
tb = TB()
run_simulation(tb, tb.test(), vcd_name="protocol.vcd")
def test_axi2csr(data_width):
dut = AXI2CSR(bus_csr=csr_bus.Interface(data_width=data_width))
dut.submodules.sram = csr_bus.SRAM(
0x100, 0, bus=csr_bus.Interface(data_width=data_width))
dut.submodules += csr_bus.Interconnect(dut.csr, [dut.sram.bus])
write_aw = partial(dut.bus.write_aw,
size=burst_size(dut.bus.data_width // 8),
len_=0,
burst=Burst.fixed)
write_w = dut.bus.write_w
read_b = dut.bus.read_b
write_ar = partial(dut.bus.write_ar,
size=burst_size(dut.bus.data_width // 8),
len_=0,
burst=Burst.fixed)
read_r = dut.bus.read_r
w_mon = partial(csr_w_mon, dut.csr)
def testbench_axi2csr():
i = dut.bus
def aw_channel():
assert (yield i.aw.ready) == 1
yield from write_aw(0x01, 0x00)
yield from write_aw(0x02, 0x04)
yield from write_aw(0x03, 0x08)
yield from write_aw(0x04, 0x0c)
yield from write_aw(0x05, 0x40)
def w_channel():
yield from write_w(0, 0x11, strb=1)
yield from write_w(0, 0x22, strb=1)
yield from write_w(0, 0x33, strb=1)
yield from write_w(0, 0x44, strb=1)
yield from write_w(0, 0x11223344)
def b_channel():
assert attrgetter_b((yield from read_b())) == (0x01, okay)
assert attrgetter_b((yield from read_b())) == (0x02, okay)
assert attrgetter_b((yield from read_b())) == (0x03, okay)
assert attrgetter_b((yield from read_b())) == (0x04, okay)
assert attrgetter_b((yield from read_b())) == (0x05, okay)
def ar_channel():
# ensure data was actually written
assert attrgetter_csr_w_mon((yield from w_mon())) == (0x00, 0x11)
assert attrgetter_csr_w_mon((yield from w_mon())) == (0x01, 0x22)
assert attrgetter_csr_w_mon((yield from w_mon())) == (0x02, 0x33)
assert attrgetter_csr_w_mon((yield from w_mon())) == (0x03, 0x44)
if data_width == 8:
assert attrgetter_csr_w_mon((yield from
w_mon())) == (0x10, 0x44)
elif data_width == 16:
assert attrgetter_csr_w_mon((yield from
w_mon())) == (0x10, 0x3344)
# ok, read it now
yield from write_ar(0x11, 0x00)
yield from write_ar(0x22, 0x04)
yield from write_ar(0x33, 0x08)
yield from write_ar(0x44, 0x0c)
yield from write_ar(0x55, 0x40)
def r_channel():
assert attrgetter_r((yield from read_r())) == (0x11, 0x11, okay, 1)
assert attrgetter_r((yield from read_r())) == (0x22, 0x22, okay, 1)
assert attrgetter_r((yield from read_r())) == (0x33, 0x33, okay, 1)
assert attrgetter_r((yield from read_r())) == (0x44, 0x44, okay, 1)
if data_width == 8:
assert attrgetter_r((yield from
read_r())) == (0x55, 0x44, okay, 1)
elif data_width == 16:
assert attrgetter_r((yield from
read_r())) == (0x55, 0x3344, okay, 1)
return [
aw_channel(),
w_channel(),
b_channel(),
r_channel(),
ar_channel(),
]
run_simulation(dut,
testbench_axi2csr(),
vcd_name=file_tmp_folder("test_axi2csr.vcd"))
def test_axi_wrshim():
dut = wrshim.AxiWrshim()
def testbench_wrshim(wrshim):
i, o = dut.m_axi_i, dut.m_axi_o
assert (yield o.aw.valid) == 0
assert (yield i.aw.ready) == 0
assert (yield o.w.valid) == 0
assert (yield i.w.ready) == 0
yield i.aw.valid.eq(1)
yield o.aw.ready.eq(1)
yield i.w.last.eq(1)
yield
assert (yield o.aw.valid) == 1
assert (yield i.aw.ready) == 1
assert (yield o.w.valid) == 0
assert (yield i.w.ready) == 0
yield o.w.ready.eq(1)
yield
assert (yield o.aw.valid) == 1
assert (yield i.aw.ready) == 1
assert (yield o.w.valid) == 0
assert (yield i.w.ready) == 1
yield i.w.valid.eq(1)
yield
assert (yield o.aw.valid) == 1
assert (yield i.aw.ready) == 1
assert (yield o.w.valid) == 1
assert (yield i.w.ready) == 1
yield i.aw.valid.eq(0)
yield i.w.valid.eq(0)
yield
assert (yield o.aw.valid) == 0
assert (yield i.aw.ready) == 1
assert (yield o.w.valid) == 0
assert (yield i.w.ready) == 1
yield i.aw.addr.eq(0x5550)
yield i.w.strb.eq(0x1)
yield
assert (yield o.aw.addr) == 0x5550
assert (yield o.aw.size) == 0x0
yield i.w.strb.eq(0x2)
yield
assert (yield o.aw.addr) == 0x5551
assert (yield o.aw.size) == 0x0
yield i.w.strb.eq(0x4)
yield
assert (yield o.aw.addr) == 0x5552
assert (yield o.aw.size) == 0x0
yield i.w.strb.eq(0x8)
yield
assert (yield o.aw.addr) == 0x5553
assert (yield o.aw.size) == 0x0
yield i.w.strb.eq(0x3)
yield
assert (yield o.aw.addr) == 0x5550
assert (yield o.aw.size) == 0x1
yield i.w.strb.eq(0xc)
yield
assert (yield o.aw.addr) == 0x5552
assert (yield o.aw.size) == 0x1
yield i.aw.size.eq(0x2)
yield i.w.strb.eq(0x0)
yield
assert (yield o.aw.addr) == 0x5550
assert (yield o.aw.size) == 0x2
run_simulation(dut, testbench_wrshim(dut), vcd_name="wrshim.vcd")
def test_axilite2csr():
class CSRHolder(Module, csr.AutoCSR):
def __init__(self):
self.foo = csr.CSRStorage(32, reset=1)
self.bar = csr.CSRStorage(32, reset=1)
class Fixture(Module):
def __init__(self):
self.csr = csr_bus.Interface(data_width=32, address_width=12)
self.axi = Interface(data_width=32, address_width=14)
self.submodules.holder = CSRHolder()
self.submodules.dut = AXILite2CSR(self.axi, self.csr)
self.submodules.csrbankarray = csr_bus.CSRBankArray(
self, self.map_csr, data_width=32, address_width=12)
self.submodules.csrcon = csr_bus.Interconnect(
self.csr, self.csrbankarray.get_buses())
def map_csr(self, name, memory):
return {
'holder': 0,
}[name]
def testbench_write_read(dut):
axi = dut.axi
for _ in range(8):
yield
# Write test
yield axi.aw.valid.eq(1)
yield axi.aw.addr.eq(4)
yield axi.w.valid.eq(1)
yield axi.b.ready.eq(1)
yield axi.w.data.eq(0x2137)
while (yield axi.aw.ready) != 1:
yield
while (yield axi.w.ready) != 1:
yield
yield axi.aw.valid.eq(0)
yield axi.w.valid.eq(0)
for _ in range(8):
yield
# Read test
yield axi.ar.valid.eq(1)
yield axi.r.ready.eq(1)
yield axi.ar.addr.eq(4)
while (yield axi.ar.ready != 1):
yield
yield axi.ar.valid.eq(0)
while (yield axi.r.valid != 1):
yield
yield axi.r.ready.eq(0)
read = yield axi.r.data
assert read == 0x2137
for _ in range(8):
yield
def testbench_simultaneous(dut):
axi = dut.axi
for _ in range(8):
yield
# Write
yield axi.aw.valid.eq(1)
yield axi.aw.addr.eq(2)
yield axi.w.valid.eq(1)
yield axi.b.ready.eq(1)
yield axi.w.data.eq(0x2137)
# Read
yield axi.ar.valid.eq(1)
yield axi.r.ready.eq(1)
yield axi.ar.addr.eq(2)
yield
yield
is_reading = yield axi.ar.ready
is_writing = yield axi.aw.ready
assert is_reading
assert not is_writing
fixture = Fixture()
run_simulation(fixture, testbench_write_read(fixture.dut), vcd_name='axi-write-read.vcd')
fixture = Fixture()
run_simulation(fixture, testbench_simultaneous(fixture.dut), vcd_name='axi-simultaneous.vcd')
version=str(VERSION_MAJOR) + "." + str(VERSION_MINOR),
help="Show current version")
parser.add_argument("--test", action="store_true", help="Run as testbench")
args = parser.parse_args()
# Add all the dependencies' base paths into the Python path.
base_dir = os.path.dirname(__file__)
deps_dir = os.path.join(base_dir, "deps")
for dep in os.listdir(deps_dir):
sys.path.append(os.path.join(deps_dir, dep))
from fomu_platform import FomuPlatform
from fomu_soc import Fomu
platform = FomuPlatform(revision=args.revision)
soc = Fomu(platform)
if not args.test:
output_dir = os.path.join(base_dir, "build")
platform.build(soc)
else:
from migen.sim import run_simulation
def testbench():
yield soc.cd_sys.clk
yield soc.cd_sys.rst
yield soc.address_bus
yield
run_simulation(soc, testbench())
