def add_pa_out_port(self, name: str, t: Union[Type, BaseDeltaType]):
"""Add output protocol adaptor v2.
Parameters
----------
type_ : Union[Type, BaseDeltaType]
Data type.
Returns
-------
migen.Record
.. todo::
Possibly use Size for data/valid/ready instead of int.
"""
df_t = as_delta_type(t)
if isinstance(df_t, Optional):
raise DeltaTypeError('out_port cannot be Optional')
out_port = migen.Record([("data", df_t.size.val, migen.DIR_S_TO_M),
("valid", 1, migen.DIR_S_TO_M),
("ready", 1, migen.DIR_M_TO_S)])
self._dut.out_ports.append((name, out_port, t))
return out_port
def add_pa_in_port(self, name: str, t: Optional):
"""Add input protocol adaptor v2.
Parameters
----------
t : Optional
Data type must be marked with Optional.
Returns
-------
migen.Record
.. todo::
Possibly use Size for data/valid/ready instead of int.
"""
if isinstance(t, Optional):
df_t = t.type
else:
raise DeltaTypeError('Migen works only with optional inputs.\n'
'Please use Optional wrapper.')
in_port = migen.Record([("data", df_t.size.val, migen.DIR_M_TO_S),
("valid", 1, migen.DIR_M_TO_S),
("ready", 1, migen.DIR_S_TO_M)])
self._dut.in_ports.append((name, in_port, t))
return in_port
def __init__(self, spi=None, bits=32):
self.jtag = mg.Record([
("sel", 1),
("shift", 1),
("capture", 1),
("tck", 1),
("tdi", 1),
("tdo", 1),
])
self.cs_n = mg.TSTriple()
self.clk = mg.TSTriple()
self.mosi = mg.TSTriple()
self.miso = mg.TSTriple()
# # #
self.cs_n.o.reset = mg.Constant(1)
self.submodules.fsm = fsm = mg.FSM("IDLE")
en = mg.Signal()
bits = mg.Signal(bits, reset_less=True)
head = mg.Signal(max=len(bits), reset=len(bits) - 1)
self.clock_domains.cd_sys = mg.ClockDomain()
self.clock_domains.cd_rise = mg.ClockDomain(reset_less=True)
if spi is not None:
self.specials += [
self.cs_n.get_tristate(spi.cs_n),
self.mosi.get_tristate(spi.mosi),
self.miso.get_tristate(spi.miso),
]
if hasattr(spi, "clk"): # 7 Series drive it fixed
self.specials += self.clk.get_tristate(spi.clk)
self.comb += [
en.eq(self.jtag.sel & self.jtag.shift),
self.cd_sys.rst.eq(self.jtag.sel & self.jtag.capture),
self.cd_sys.clk.eq(~self.jtag.tck),
self.cd_rise.clk.eq(self.jtag.tck),
self.cs_n.oe.eq(en),
self.clk.oe.eq(en),
self.mosi.oe.eq(en),
self.miso.oe.eq(0),
self.clk.o.eq(self.jtag.tck & ~self.cs_n.o),
self.mosi.o.eq(self.jtag.tdi),
]
# Some (Xilinx) bscan cells register TDO (from the fabric) on falling
# TCK and output it (externally).
# SPI requires sampling on rising CLK. This leads to one cycle of
# latency.
self.sync.rise += self.jtag.tdo.eq(self.miso.i)
fsm.act("IDLE", mg.If(self.jtag.tdi, mg.NextState("HEAD")))
fsm.act("HEAD", mg.If(head == 0, mg.NextState("XFER")))
fsm.act(
"XFER",
mg.If(bits == 0, mg.NextState("IDLE")),
self.cs_n.o.eq(0),
)
self.sync += [
mg.If(fsm.ongoing("HEAD"), bits.eq(mg.Cat(self.jtag.tdi, bits)),
head.eq(head - 1)),
mg.If(fsm.ongoing("XFER"), bits.eq(bits - 1))
]
def __init__(self, spi=None, bits=32):
self.jtag = mg.Record([
("sel", 1),
("shift", 1),
("capture", 1),
("tck", 1),
("tdi", 1),
("tdo", 1),
])
self.cs_n = mg.TSTriple()
self.clk = mg.TSTriple()
self.mosi = mg.TSTriple()
self.miso = mg.TSTriple()
# # #
self.cs_n.o.reset = mg.Constant(1)
self.mosi.o.reset_less = True
bits = mg.Signal(bits, reset_less=True)
head = mg.Signal(max=len(bits), reset=len(bits) - 1)
self.clock_domains.cd_sys = mg.ClockDomain()
self.submodules.fsm = mg.FSM("IDLE")
if spi is not None:
self.specials += [
self.cs_n.get_tristate(spi.cs_n),
self.mosi.get_tristate(spi.mosi),
self.miso.get_tristate(spi.miso),
]
if hasattr(spi, "clk"): # 7 Series drive it fixed
self.specials += self.clk.get_tristate(spi.clk)
# self.specials += io.DDROutput(1, 0, spi.clk, self.clk.o)
self.comb += [
self.cd_sys.rst.eq(self.jtag.sel & self.jtag.capture),
self.cd_sys.clk.eq(self.jtag.tck),
self.cs_n.oe.eq(self.jtag.sel),
self.clk.oe.eq(self.jtag.sel),
self.mosi.oe.eq(self.jtag.sel),
self.miso.oe.eq(0),
# Do not suppress CLK toggles outside CS_N asserted.
# Xilinx USRCCLK0 requires three dummy cycles to do anything
# https://www.xilinx.com/support/answers/52626.html
# This is fine since CS_N changes only on falling CLK.
self.clk.o.eq(~self.jtag.tck),
self.jtag.tdo.eq(self.miso.i),
]
# Latency calculation (in half cycles):
# 0 (falling TCK, rising CLK):
# JTAG adapter: set TDI
# 1 (rising TCK, falling CLK):
# JTAG2SPI: sample TDI -> set MOSI
# SPI: set MISO
# 2 (falling TCK, rising CLK):
# SPI: sample MOSI
# JTAG2SPI (BSCAN primitive): sample MISO -> set TDO
# 3 (rising TCK, falling CLK):
# JTAG adapter: sample TDO
self.fsm.act(
"IDLE",
mg.If(self.jtag.tdi & self.jtag.sel & self.jtag.shift,
mg.NextState("HEAD")))
self.fsm.act("HEAD", mg.If(head == 0, mg.NextState("XFER")))
self.fsm.act(
"XFER",
mg.If(bits == 0, mg.NextState("IDLE")),
)
self.sync += [
self.mosi.o.eq(self.jtag.tdi),
self.cs_n.o.eq(~self.fsm.ongoing("XFER")),
mg.If(self.fsm.ongoing("HEAD"),
bits.eq(mg.Cat(self.jtag.tdi, bits)), head.eq(head - 1)),
mg.If(self.fsm.ongoing("XFER"), bits.eq(bits - 1))
]
def __init__(self, z=18, x=15, zl=9, xd=4, backoff=None, share_lut=None):
self.latency = 0 # computed later
self.z = mg.Signal(z) # input phase
self.x = mg.Signal((x + 1, True), reset_less=True) # output cos(z)
self.y = mg.Signal((x + 1, True), reset_less=True) # output sin(z)
###
if backoff is None:
backoff = min(3, (1 << x - 1) - 1)
self.x_max = (1 << x) - backoff
# LUT depth
if zl is None:
zl = z - 3
assert zl >= 0
# generate the cos/sin LUT
a = np.exp(1j * np.pi / 4 / (1 << zl) * (np.arange(1 << zl) + .5))
cs = np.round(self.x_max * a)
csd = np.round(np.pi / 4 / (1 << x - xd) * cs)
lut_init = []
for csi, csdi in zip(cs, csd):
# save a bit by noticing that cos(z) > 1/2 for 0 < z < pi/4
xy = csi - (1 << x - 1)
xi, yi = int(xy.real), int(xy.imag)
assert 0 <= xi < 1 << x - 1, csi
assert 0 <= yi < 1 << x, csi
lut_init.append(xi | (yi << x - 1))
if xd:
# derivative LUT
# save a bit again
xyd = csdi - (1 << xd - 1)
xid, yid = int(xyd.real), int(xyd.imag)
assert 0 <= xid < 1 << xd - 1, csdi
assert 0 <= yid < 1 << xd, csdi
lut_init[-1] |= (xid << 2 * x - 1) | (yid << 2 * x + xd - 2)
# LUT ROM
mem_layout = [("x", x - 1), ("y", x)]
if xd:
mem_layout.extend([("xd", xd - 1), ("yd", xd)])
lut_data = mg.Record(mem_layout, reset_less=True)
assert len(lut_init) == 1 << zl
assert all(0 <= _ < 1 << len(lut_data) for _ in lut_init)
logger.info("CosSin LUT {} bit deep, {} bit wide".format(
zl, len(lut_data)))
if share_lut is not None:
assert all(a == b for a, b in zip(share_lut.init, lut_init))
self.lut = share_lut
else:
self.lut = mg.Memory(len(lut_data), 1 << zl, init=lut_init)
self.specials += self.lut
lut_port = self.lut.get_port()
self.specials += lut_port
self.sync += [
# use BRAM output data register
lut_data.raw_bits().eq(lut_port.dat_r),
]
self.latency += 1 # mem dat_r output register
# compute LUT address
# 3 MSBs: octant
# LSBs: phase, maped into first octant
za = mg.Signal(z - 3)
self.comb += [
za.eq(
mg.Mux(self.z[-3], (1 << z - 3) - 1 - self.z[:-3],
self.z[:-3])),
lut_port.adr.eq(za[-zl:]),
]
self.latency += 1 # mem address register
if xd: # apply linear interpolation
zk = z - 3 - zl
zd = mg.Signal((zk + 1, True), reset_less=True)
self.comb += zd.eq(za[:zk] - (1 << zk - 1) + self.z[-3])
zd = self.pipe(zd, self.latency)
# add a rounding bias
zq = z - 3 - x + xd
assert zq > 0
qb = (1 << zq - 1) - 1
lxd = mg.Signal((xd + zk, True), reset_less=True)
lyd = mg.Signal((xd + zk, True), reset_less=True)
self.sync += [
lxd.eq(zd * (lut_data.xd | (1 << xd - 1))),
lyd.eq(zd * lut_data.yd),
]
x1 = self.pipe(
self.pipe(lut_data.x | (1 << x - 1), 1) - ((lyd + qb) >> zq),
1)
y1 = self.pipe(self.pipe(lut_data.y, 1) + ((lxd + qb) >> zq), 1)
self.latency += 2
else:
x1 = self.pipe(lut_data.x | (1 << x - 1), 0)
y1 = self.pipe(lut_data.y, 0)
# unmap octant
zq = self.pipe(
mg.Cat(self.z[-3] ^ self.z[-2], self.z[-2] ^ self.z[-1],
self.z[-1]), self.latency)
# intermediate unmapping signals
x2 = self.pipe(mg.Mux(zq[0], y1, x1), 0)
y2 = self.pipe(mg.Mux(zq[0], x1, y1), 0)
self.comb += [
self.x.eq(mg.Mux(zq[1], -x2, x2)),
self.y.eq(mg.Mux(zq[2], -y2, y2)),
]