def __init__(self, **kwargs):
super().__init__(**kwargs)
self.platform.add_extension(ltc.ltc_pads)
self.submodules.lvds = LTCPhy(self.platform, self.sys_clk_freq, 120e6)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.lvds.pads_dco)
# Frequency counter for received sample clock
self.submodules.f_sample = FreqMeter(self.sys_clk_freq)
self.comb += self.f_sample.clk.eq(ClockSignal("sample"))
spi_pads = self.platform.request("LTC_SPI")
self.submodules.spi = spi.SPIMaster(spi_pads, 16, self.sys_clk_freq,
self.sys_clk_freq / 32)
width, depth = 16 * 2, 8192
storage = Memory(width, depth, init=[0x1234, 0xCAFECAFE, 0x00C0FFEE])
self.specials += storage
self.submodules.adc_data_buffer = wishbone.SRAM(storage,
read_only=True)
port = storage.get_port(write_capable=True, clock_domain="sample")
self.register_mem("adc_data_buffer", 0x10000000,
self.adc_data_buffer.bus, depth * 8)
self.specials += port
self.submodules.acq = DumpToRAM(width, depth, port)
self.sync.sample += self.acq.adc_data.eq(
Cat(Signal(2), self.lvds.sample_outs[0], Signal(2),
self.lvds.sample_outs[1]))
self.sync += self.lvds.init_running.eq(self.ctrl.reset)
for p in LTCSocDev.csr_peripherals:
self.add_csr(p)
def __init__(self, vga, sin_t, col_t):
pos1 = Signal(bits_sign=9)
pos3 = Signal(bits_sign=9)
tpos1 = Signal(bits_sign=9)
tpos2 = Signal(bits_sign=9)
tpos3 = Signal(bits_sign=9)
tpos4 = Signal(bits_sign=9)
index = Signal(bits_sign=6)
count = Signal()
self.specials.col_t = Memory(4, 256, init=col_t)
self.specials.sin_t = Memory(32, 512, init=sin_t)
sin_p = self.sin_t.get_port(async_read=True)
col_p = self.col_t.get_port(async_read=True)
self.specials += sin_p
self.specials += col_p
self.ios = {sin_p.adr, sin_p.dat_r, col_p.adr, col_p.dat_r}
sin = Signal(bits_sign=(32, True))
self.sync += If(vga.hc < VGA.hpixels - 1, [
If((vga.hc >= VGA.hbp) & (vga.hc < VGA.hfp), [
tpos1.eq(tpos1 + 5),
tpos2.eq(tpos2 + 3)
])
]).Else([
If(vga.vc < VGA.vlines - 1, [
If((vga.vc >= VGA.vbp) & (vga.vc < VGA.vfp), [
tpos1.eq(pos1 + 5),
tpos2.eq(3),
tpos3.eq(tpos3 + 1),
tpos4.eq(tpos4 + 3)
])
]).Else([
pos1.eq(pos1 + 9),
pos3.eq(pos3 + 8),
tpos4.eq(0),
tpos3.eq(0),
count.eq(count + 1)
])
])
self.sync += If((vga.vc >= VGA.vbp) & (vga.vc < VGA.vfp), [
If((vga.hc >= VGA.hbp) & (vga.hc < VGA.hfp), [
calc_index(tpos1, sin, sin_p, acc=False, zero=True),
calc_index(tpos2, sin, sin_p),
calc_index(tpos3, sin, sin_p),
calc_index(tpos4, sin, sin_p),
index.eq(sin >> 4),
col_p.adr.eq(index),
Cat(vga.color.g1, vga.color.g0, vga.color.r1, vga.color.r0).eq(col_p.dat_r)
]).Else(vga.color.black())
]).Else(vga.color.black())
def __init__(self, index, data: list, width: int = None, readonly=False):
"""
A read-only memory module.
Args:
index (Signal): the signal to provide the index
data (list): values of the rom.
width (int or NoneType): the bit-width of each value, or None to
automatically infer this from the data.
readonly (bool): if True, a ROM instead of RAM is created.
Output signals:
value: a signal with the ROM value at index.
"""
width, depth = self._get_width_and_depth(data, width)
self.value = Signal(width, reset=0)
###
self.specials.memory = Memory(width=width, depth=depth, init=data)
self.specials.port = self.memory.get_port(write_capable=not readonly,
we_granularity=False)
self.comb += [
self.port.adr.eq(index),
self.value.eq(self.port.dat_r),
]
self.width = width
self.depth = depth
self.data = data
def __init__(self, output):
self.specials.rom = Memory(8, 16384, rom_image)
rom_port = self.rom.get_port(write_capable=False)
self.specials += rom_port
counter = Signal(16)
self.sync += counter.eq(counter + 1)
self.comb += rom_port.adr.eq(counter)
self.comb += output.eq(rom_port.dat_r)
def migen_body(self, template):
# creation of input/output ports
shot_completed = template.add_pa_in_port('shot_completed',
dl.DOptional(dl.DBool()))
hal_result = template.add_pa_in_port(
'hal_result',
dl.DOptional(dl.DUInt(dl.DSize(32)))
)
agg_result = template.add_pa_out_port('agg_result',
dl.DInt(dl.DSize(32)))
# Completed is currently returning a simple 0/1 value but we make space
# for an error code to be returned e.g. 255, 0b11111111 can be in the
# future used to represent an error.
completed = template.add_pa_out_port('completed', dl.DInt(dl.DSize(8)))
next_angle = template.add_pa_out_port(
'next_angle',
dl.DRaw(dl.DUInt(dl.DSize(ANGLE_MEMORY_WIDTH)))
)
# generate a ROM of 10-bit angle values
angles = generate_angles(RESOLUTION)
self.specials.angle_memory = angle_memory = Memory(
ANGLE_MEMORY_WIDTH, len(angles), init=angles, name="ANGLE_ROM"
)
angle_rom_port = angle_memory.get_port(write_capable=False)
self.specials += angle_rom_port
# set up internal signals
_shots_counter = Signal(32)
_high_hal_results = Signal(32)
_reset_high_hal = Signal(1)
_angle_rom_index = Signal(RESOLUTION+1)
self.comb += (
# declare input/output ports always happy to receive/transmit data
hal_result.ready.eq(1),
shot_completed.ready.eq(1),
# align angle ROM address with ROM index signal
angle_rom_port.adr.eq(_angle_rom_index),
)
# define finite state machine for triggering angle and result signals
self.submodules.rabi_aggregator_fsm = \
rabi_aggregator_fsm = FSM(reset_state="IDLE")
# Logic to accumulate measurements
self.sync += (
If (_reset_high_hal == 1,
_high_hal_results.eq(0)
).Else (
If (hal_result.valid == 1,
If ((hal_result.data &
dl.lib.Masks.MEASUREMENTS.value) == 1,
_high_hal_results.eq(_high_hal_results + 1)
)
)
)
)
# waits for the experiment to be kicked off
rabi_aggregator_fsm.act(
"IDLE",
NextValue(agg_result.valid, 0),
NextValue(next_angle.valid, 0),
NextValue(completed.valid, 0),
NextValue(_shots_counter, 0),
NextValue(_reset_high_hal, 1),
NextState("DO_SHOTS")
)
rabi_aggregator_fsm.act(
"DO_SHOTS",
NextValue(agg_result.valid, 0),
NextValue(_reset_high_hal, 0),
If (_shots_counter == REPETITIONS,
NextState("CHECK_IF_COMPLETE"),
NextValue(_angle_rom_index, _angle_rom_index + 1),
NextValue(agg_result.data, _high_hal_results),
NextValue(agg_result.valid, 1),
NextValue(_reset_high_hal, 1),
).Else (
NextValue(next_angle.data, angle_rom_port.dat_r),
NextValue(next_angle.valid, 1),
NextState("WAIT_SHOT")
)
)
rabi_aggregator_fsm.act(
"WAIT_SHOT",
NextValue(next_angle.valid, 0),
If ((shot_completed.valid == 1) & (shot_completed.data == 1),
NextValue(_shots_counter, _shots_counter + 1),
NextState("DO_SHOTS"),
)
)
rabi_aggregator_fsm.act(
"CHECK_IF_COMPLETE",
NextState("IDLE"),
NextValue(agg_result.valid, 0),
If(_angle_rom_index == 2 ** RESOLUTION,
NextValue(completed.data, 1),
NextValue(completed.valid, 1),
)
)
def __init__(self):
self.specials.rom = Memory(16, 4096, rom_image)
rom_port = self.rom.get_port(write_capable=False)
self.specials += rom_port
self.specials.ram = Memory(8, 8192, rom_image)
ram_port = self.ram.get_port(write_capable=True)
self.specials += ram_port
program_counter = Signal(16)
self.sync += program_counter.eq(program_counter + 1)
self.comb += rom_port.adr.eq(program_counter)
accumulator = Signal(8)
op_code = Signal(3)
op_mode = Signal(3)
op_bus = Signal(2)
op_data = Signal(8)
Cat(op_bus, op_mode, op_code, op_data).eq(rom_port.dat_r)
sig_ar0 = Signal()
sig_ar0.eq((op_code == OP_SUB) | (op_code == OP_BCC))
sig_ar1 = Signal()
sig_ar1.eq((op_code == OP_OR) | (op_code == OP_XOR) | (op_code == OP_SUB))
sig_ar2 = Signal()
sig_ar2.eq((op_code == OP_LD) | (op_code == OP_OR) | (op_code == OP_XOR) | (op_code == OP_ADD) | (op_code == OP_BCC))
sig_ar3 = Signal()
sig_ar3.eq((op_code == OP_LD) | (op_code == OP_AND) | (op_code == OP_OR) | (op_code == OP_ADD))
sig_al = Signal()
sig_al.eq((op_code == OP_BCC) | (~op_code[2]))
sig_xl = Signal()
sig_xl.eq(op_mode != MOD_DX)
sig_yl = Signal()
sig_yl.eq(op_mode != MOD_DY)
sig_ix = Signal()
sig_ix.eq(op_mode == MOD_YXOUT)
sig_eh = Signal()
sig_eh.eq((op_mode != MOD_YDAC) & (op_mode != MOD_YXAC) & (op_mode != MOD_YXOUT))
sig_el = Signal()
sig_el.eq((op_mode != MOD_XAC) & (op_mode != MOD_YXAC) & (op_mode != MOD_YXOUT))
sig_ol = Signal()
sig_ol.eq(((op_mode != MOD_DOUT) & (op_mode != MOD_YXOUT)) | (op_code == OP_ST))
sig_ld = Signal()
sig_ld.eq(((op_mode != MOD_DAC) & (op_mode != MOD_XAC) & (op_mode != MOD_YDAC) & (op_mode != MOD_YXAC)) | (op_code == OP_ST))
# this isn't quite right, in the schematic it's all about AC7 and the
# carry-out of the ALU adder, hmmm.
sig_cond = Signal()
sig_cond.eq(
(op_mode == MOD_JMP) | (op_mode == MOD_BRA) |
((op_mode == MOD_BNE) & (accumulator != 0)) |
((op_mode == MOD_BEQ) & (accumulator == 0)) |
((op_mode == MOD_BLT) & (accumulator < 0)) |
((op_mode == MOD_BGT) & (accumulator > 0)) |
((op_mode == MOD_BLE) & (accumulator <= 0)) |
((op_mode == MOD_BGE) & (accumulator >= 0))
)
sig_ph = Signal()
sig_ph.eq((op_code == OP_BCC) & (op_mode == MOD_JMP))
sig_pl = Signal()
sig_pl.eq((op_code == OP_BCC) & sig_cond)
data_bus = Signal(8)
Case(op_bus, {
0: data_bus.eq(op_data),
1: data_bus.eq(ram_port.dat_r),
2: data_bus.eq(accumulator),
3: data_bus.eq(dinput),
})
register_x = Signal(8)
register_y = Signal(8)
ram_addr_l = Signal(8)
ram_addr_h = Signal(8)
ram_addr_l.eq(Mux(sig_el, register_x, data_bus))
ram_addr_h.eq(Mux(sig_eh, register_y, 0))
self.comb += ram_port.adr.eq(Cat(ram_addr_l, ram_addr_h))
self.comb += ram_port.we.eq(rom_port.dat_r[0])
self.comb += ram_port.dat_w.eq(rom_port.dat_r[0:8])
self.comb += output.eq(ram_port.dat_r[0:8])