def test_upscaler():
i = axi.Interface()
dw = i.data_width
dut = stream.Converter(8, dw)
source, sink = dut.source, dut.sink
write = partial(write_data, sink)
read = partial(read_data, source)
def testbench_upscaler():
def push():
yield from write(0x11)
yield from write(0x22)
yield from write(0x33)
yield from write(0x44)
yield from write(0x55)
yield from write(0x66)
yield from write(0x77)
yield from write(0x88)
yield from write(0x99, eop=1)
def pull():
yield source.ack.eq(1)
assert (yield from read()) == 0x44332211
yield
assert (yield from read()) == 0x88776655
yield
assert (yield from read()) & 0xff == 0x99
return [
push(),
pull(),
]
run_simulation(dut, testbench_upscaler())
def test_downscaler():
i = axi.Interface()
dw = i.data_width
dut = stream.Converter(dw, 8)
source, sink = dut.source, dut.sink
write = partial(write_data, sink)
read = partial(read_data, source)
def testbench_downscaler():
def push():
yield from write(0x44332211)
yield from write(0x88776655, eop=True)
def pull():
yield source.ack.eq(1)
assert (yield from read()) == 0x11
yield
assert (yield from read()) == 0x22
yield
assert (yield from read()) == 0x33
yield
assert (yield from read()) == 0x44
yield
assert (yield from read()) == 0x55
yield
assert (yield from read()) == 0x66
yield
assert (yield from read()) == 0x77
yield
assert (yield from read()) == 0x88
assert (yield source.eop) == 1
return [
push(),
pull(),
]
run_simulation(dut,
testbench_downscaler(),
vcd_name=file_tmp_folder("test_downscaler.vcd"))
def test_reader():
i = axi.Interface()
dw = i.data_width
dut = Reader(i)
dut.submodules.downscaler = stream.Converter(dw, 8)
dut.comb += dut.source.connect(dut.downscaler.sink)
source, sink = dut.downscaler.source, dut.sink
request = partial(request_addr, sink)
read = partial(read_data, source)
def testbench_reader():
def push_addr():
yield from request(0x11223344, eop=True)
def pull_data():
yield source.ack.eq(1)
assert (yield from read()) == 0x04
yield
assert (yield from read()) == 0x03
yield
assert (yield from read()) == 0x02
yield
assert (yield from read()) == 0x01
assert (yield source.eop) == 1
def ar_and_r_channel():
assert (yield from i.read_ar()).addr == 0x11223344
yield from i.write_r(0x55, 0x01020304, last=1)
return [
push_addr(),
pull_data(),
ar_and_r_channel(),
]
run_simulation(dut,
testbench_reader(),
vcd_name=file_tmp_folder("test_reader.vcd"))
def __init__(self, bus=None, user=None, trigger_stb=None):
self.bus = bus or axi.Interface(data_width=64)
self.addr_base = CSRStorage(32)
self.trig_count = CSRStatus(32)
self.write_count = CSRStatus(32)
# Dout : Data received from CPU, output by DMA module
# Din : Data driven into DMA module, written into CPU
# When stb assert, index shows word being read/written, dout/din holds
# data
#
# Cycle:
# trigger_stb pulsed at start
# Then out_burst_len words are strobed out of dout
# Then, when din_ready is high, in_burst_len words are strobed in to din
self.dout_stb = Signal()
self.din_stb = Signal()
self.dout_index = Signal(max=16)
self.din_index = Signal(max=16)
self.din_ready = Signal()
self.dout = Signal(64)
self.din = Signal(64)
self.out_burst_len = Signal(max=16)
self.in_burst_len = Signal(max=16)
###
self.trigger_stb = trigger_stb
self.sync += If(trigger_stb, self.trig_count.status.eq(self.trig_count.status+1))
if user:
self.comb += user.aruser.eq(0x1f)
self.comb += user.awuser.eq(0x1f)
ar, aw, w, r, b = attrgetter("ar", "aw", "w", "r", "b")(self.bus)
### Read
self.comb += [
ar.addr.eq(self.addr_base.storage),
self.dout.eq(r.data),
r.ready.eq(1),
ar.burst.eq(axi.Burst.incr.value),
ar.len.eq(self.out_burst_len-1), # Number of transfers in burst (0->1 transfer, 1->2 transfers...)
ar.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits
ar.cache.eq(0xf),
]
# read control
self.submodules.read_fsm = read_fsm = FSM(reset_state="IDLE")
read_fsm.act("IDLE",
If(trigger_stb,
ar.valid.eq(1),
If(ar.ready,
NextState("READ")
).Else(
NextState("READ_START")
)
)
)
read_fsm.act("READ_START",
ar.valid.eq(1),
If(ar.ready,
NextState("READ"),
)
)
read_fsm.act("READ",
ar.valid.eq(0),
If(r.last & r.valid,
NextState("IDLE")
)
)
self.sync += [
If(read_fsm.ongoing("IDLE"),
self.dout_index.eq(0)
).Else(If(r.valid & read_fsm.ongoing("READ"),
self.dout_index.eq(self.dout_index+1)
)
)
]
self.comb += self.dout_stb.eq(r.valid & r.ready)
### Write
self.comb += [
w.data.eq(self.din),
aw.addr.eq(self.addr_base.storage+32), # Write to next cache line
w.strb.eq(0xff),
aw.burst.eq(axi.Burst.incr.value),
aw.len.eq(self.in_burst_len-1), # Number of transfers in burst minus 1
aw.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits
aw.cache.eq(0xf),
b.ready.eq(1),
]
# write control
self.submodules.write_fsm = write_fsm = FSM(reset_state="IDLE")
write_fsm.act("IDLE",
w.valid.eq(0),
aw.valid.eq(0),
If(trigger_stb,
aw.valid.eq(1),
If(aw.ready, # assumes aw.ready is not randomly deasserted
NextState("DATA_WAIT")
).Else(
NextState("AW_READY_WAIT")
)
)
)
write_fsm.act("AW_READY_WAIT",
aw.valid.eq(1),
If(aw.ready,
NextState("DATA_WAIT"),
)
)
write_fsm.act("DATA_WAIT",
aw.valid.eq(0),
If(self.din_ready,
w.valid.eq(1),
NextState("WRITE")
)
)
write_fsm.act("WRITE",
w.valid.eq(1),
If(w.ready & w.last,
NextState("IDLE")
)
)
self.sync += If(w.ready & w.valid, self.write_count.status.eq(self.write_count.status+1))
self.sync += [
If(write_fsm.ongoing("IDLE"),
self.din_index.eq(0)
),
If(w.ready & w.valid, self.din_index.eq(self.din_index+1))
]
self.comb += [
w.last.eq(0),
If(self.din_index==aw.len, w.last.eq(1))
]
self.comb += self.din_stb.eq(w.valid & w.ready)
def __init__(self, bus=None):
self.bus = bus or axi.Interface(data_width=64)
self.addr_base = CSRStorage(32)
self.n_bursts = CSRStorage(32) # Number of bursts to do -1
self.trigger = CSR(1)
self.n_cycles = CSRStatus(32)
self.status = CSRStatus(1)
self.n_read = CSRStatus(32)
self.dout = Signal(32)
self.dout_stb = Signal()
###
ar, aw, w, r, b = attrgetter("ar", "aw", "w", "r", "b")(self.bus)
BURST_LEN = 16
trigger_stb = self.trigger.re
addr = Signal(32)
read_request_accepted = Signal() # Asserted when the read request has been accepted
read_request = Signal()
n_done = Signal(32)
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
If(trigger_stb,
NextValue(addr, self.addr_base.storage),
NextValue(read_request, 1),
NextState("RUNNING")
)
)
fsm.act("RUNNING",
If(read_request_accepted,
NextValue(addr, addr+BURST_LEN),
NextValue(n_done, n_done+1),
If(n_done == self.n_bursts.storage,
NextState("IDLE"),
NextValue(read_request, 0)
)
)
)
### Read
self.comb += [
ar.addr.eq(self.addr_base.storage),
self.dout.eq(r.data),
r.ready.eq(1),
ar.burst.eq(axi.Burst.incr.value),
ar.len.eq(BURST_LEN-1), # Number of transfers in burst (0->1 transfer, 1->2 transfers...)
ar.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits
ar.cache.eq(0xf),
]
# read control
self.comb += read_request_accepted.eq(ar.ready & ar.valid)
self.submodules.read_fsm = read_fsm = FSM(reset_state="IDLE")
read_fsm.act("IDLE",
If(read_request,
ar.valid.eq(1),
If(ar.ready,
NextState("WAIT")
).Else(
NextState("READ_START")
)
)
)
read_fsm.act("READ_START",
ar.valid.eq(1),
If(ar.ready,
NextState("WAIT"),
)
)
read_fsm.act("WAIT",
NextState("IDLE")
)
self.comb += self.dout_stb.eq(r.valid & r.ready)
n_bursts_received = Signal(32)
self.sync += [
If(trigger_stb, n_bursts_received.eq(0)),
If(self.dout_stb & r.last, n_bursts_received.eq(n_bursts_received+1))
]
self.sync += [
If(trigger_stb, self.status.status.eq(1)),
If(n_bursts_received==self.n_bursts.storage+1, self.status.status.eq(0))
]
self.sync += [
If(self.status.status, self.n_cycles.status.eq(self.n_cycles.status+1)),
If(trigger_stb, self.n_cycles.status.eq(0))
]
self.sync += [
If(self.dout_stb, self.n_read.status.eq(self.n_read.status+1)),
If(trigger_stb, self.n_read.status.eq(0))
]