def wids(HL):
if HL == 0:
return ''
H = HL[0]
L = HL[1]
if (H == -1):
return ''
else:
return '[%s:%s]' % (pr_expr(H), pr_expr(L))
def wids(Wid):
if is_double_def(Wid):
if (Wid[0]=='packed'):
return '%s%s'%(pr_wid(Wid[1]),pr_wid(Wid[2]))
if Wid==0:
return ''
H=Wid[0]
L=Wid[1]
if (H==-1):
return ''
else:
return '[%s:%s]'%(pr_expr(H),pr_expr(L))
def fixingModule(Mod,Env):
Defs={}
for (Dst,Src,_,_) in Mod.hard_assigns:
Sup0 = support_set(Dst,True)
Sup1 = support_set(Src,True)
for Item in Sup0+Sup1:
if Item not in Mod.parameters:
useForDefs(Item,Defs)
for (Body,When,_) in Mod.alwayses:
Sup0 = support_set(Body,True)
Sup1 = support_set(When,True)
for Item in Sup0+Sup1:
if Item not in Mod.parameters:
useForDefs(Item,Defs)
for Inst in Mod.insts:
Obj = Mod.insts[Inst]
for Pin in Obj.conns:
Sig = Obj.conns[Pin]
Sup0 = support_set(Sig,True)
for Item in Sup0:
if Item not in Mod.parameters:
useForDefs(Item,Defs)
print '>>>',Mod.Module
for Net in Defs:
if Net not in Mod.nets:
print 'net %s is not a net %s'%(Net,Defs[Net])
print 'wire %s %s;\n'%(pr_wid(Wid),pr_expr(Net))
else:
Dir,Wid = Mod.nets[Net]
print 'net %s here=%s mod=%s %s'%(Net,Defs[Net],Dir,Wid)
def recomputeDims(Sig, Oparameters, Mparameters, Mlocals, Oobj_params):
if type(Sig) is str: return Sig
y = {**Mlocals, **Oobj_params}
z = {**Oparameters, **Mparameters}
zz = {**z, **y}
if (type(Sig) is tuple) or (type(Sig) is list):
if Sig[0] == 'subbus':
if len(Sig) == 3:
print('PREXPR', Sig[2][0], module_class.pr_expr(Sig[2][0]), zz)
H = eval(str(module_class.pr_expr(Sig[2][0])), zz)
L = eval(str(Sig[2][1]), zz)
elif len(Sig) == 4:
print('PREXPR', Sig[2], module_class.pr_expr(Sig[2]), zz)
H = eval(str(module_class.pr_expr(Sig[2])), zz)
L = eval(str(Sig[3]), zz)
return ['subbus', Sig[1], H, L]
return Sig
def widsx(HL):
if HL==0:
return '1'
H=HL[0]
L=HL[1]
if (H==-1):
return '1'
else:
return '%s'%(pr_expr(int(H)-int(L)+1))
def pr_wid(Wid):
if Wid==None:
logs.log_err('wid is none error')
traceback.print_stack(None,None,logs.Flog)
return 'wid is none error!!'
if Wid==0:
return ''
if type(Wid)==types.IntType:
return '[%s:0]'%(pr_expr(Wid))
if (len(Wid)==3)and(Wid[0]=='double'):
return '%s%s'%(pr_wid(Wid[1]),pr_wid(Wid[2]))
if (len(Wid)==3)and(Wid[0]=='packed'):
return pr_wid(Wid[1])+pr_wid(Wid[2])
if len(Wid)==3:
logs.log_err('pr_wid %s'%(str(Wid)))
traceback.print_stack(None,None,logs.Flog)
return str(Wid)
return '[%s:%s]'%(pr_expr(Wid[0]),pr_expr(Wid[1]))
def dump_empty_module(Mod):
Name = Mod.Module
Fout = open('%s.empty' % (Name), 'w')
Fout.write('module %s (\n' % Name)
Ins = []
Outs = []
Sigs = Mod.nets.keys()
for Sig in Sigs:
DirHL = Mod.nets[Sig]
Dir1 = DirHL[0]
if ('input' in Dir1):
Ins.append((Sig, DirHL[0], DirHL[1]))
elif ('output' in Dir1):
Outs.append((Sig, DirHL[0], DirHL[1]))
Ins.sort()
Outs.sort()
Pref = ' '
for In, Dir, HL in Ins:
if HL == 0:
Fout.write(' %s%s %s %s\n' % (Pref, Dir, ' ', In))
else:
Fout.write(' %s%s [%s:%s] %s\n' %
(Pref, Dir, pr_expr(HL[0]), pr_expr(HL[1]), In))
Pref = ','
for Out, Dir, HL in Outs:
if 'reg' not in Dir:
Dir = '%s reg' % (Dir)
if HL == 0:
Fout.write(' %s%s %s %s\n' % (Pref, Dir, ' ', Out))
else:
Fout.write(' %s%s [%s:%s] %s\n' %
(Pref, Dir, HL[0], HL[1], Out))
Pref = ','
Fout.write(');\n')
Fout.write('initial begin\n')
for Out, Dir, HL in Outs:
Fout.write(' %s = 0;\n' % Out)
Fout.write('end\n')
Fout.write('endmodule\n')
Fout.close()
def createTb(Mod):
Fout = open('src/wrap_%s.v' % Mod.Module, 'w')
Fout.write('module wrap_%s (input incrdbg\n' % Mod.Module)
Inst = '%s dut(\n' % (Mod.Module)
Pref = ' '
Assigns = []
for Net in MUSTS:
Mod.nets[Net] = ('output reg', (31, 0))
for Net in Mod.nets:
Dir, Wid = Mod.nets[Net]
Dir = Dir.replace('reg', '')
Dir = Dir.replace(' ', '')
if 'input' in Dir:
Fout.write(' ,%s %s %s\n' %
(module_class.pr_dir(Dir), module_class.pr_wid(Wid),
module_class.pr_expr(Net)))
Inst += ' %s.%s(%s)\n' % (Pref, Net, Net)
elif Net in MUSTS:
Fout.write(' ,%s %s %s\n' %
(module_class.pr_dir('output reg'),
module_class.pr_wid(Wid), module_class.pr_expr(Net)))
else:
Fout.write(' ,%s %s %s\n' %
(module_class.pr_dir('output'),
module_class.pr_wid(Wid), module_class.pr_expr(Net)))
if 'output' not in Dir:
Assigns.append('assign %s = dut.%s;\n' % (Net, Net))
Mod.nets[Net] = 'output', Wid
elif Net not in MUSTS:
Inst += ' %s.%s(%s)\n' % (Pref, Net, Net)
Pref = ','
Fout.write(');\n')
Fout.write('%s);\n' % Inst)
for Assign in Assigns:
Fout.write(Assign)
Fout.write(HELPERS1)
Fout.close()
def dump_empty_module(Mod):
Name = Mod.Module
Fout = open('%s.empty'%(Name),'w')
Prms = []
for Prm in Mod.parameters:
This = 'parameter %s = %s\n'%(Prm,pr_expr(Mod.parameters[Prm]))
Prms.append(This)
if Prms!=[]:
Fout.write('module %s #(\n %s)\n(\n'%(Name,string.join(Prms,' ,')))
else:
Fout.write('module %s (\n'%Name)
Ins=[]
Outs=[]
Sigs = Mod.nets.keys()
for Sig in Sigs:
DirHL = Mod.nets[Sig]
Dir1 = DirHL[0]
if ('input' in Dir1):
Ins.append((Sig,DirHL[0],DirHL[1]))
elif ('output' in Dir1):
Outs.append((Sig,DirHL[0],DirHL[1]))
Ins.sort()
Outs.sort()
Pref = ' '
for In,Dir,HL in Ins:
if HL==0:
Fout.write(' %s%s %s %s\n'%(Pref,Dir,' ',In))
else:
Fout.write(' %s%s %s %s\n'%(Pref,Dir,wids(HL),In))
Pref = ','
for Out,Dir,HL in Outs:
if 'reg' not in Dir:
Dir = '%s reg'%(Dir)
if HL==0:
Fout.write(' %s%s %s %s\n'%(Pref,Dir,' ',Out))
else:
Fout.write(' %s%s %s %s\n'%(Pref,Dir,wids(HL),Out))
Pref = ','
Fout.write(');\n')
Fout.write('initial begin\n')
for Out,Dir,HL in Outs:
Fout.write(' %s = 0;\n'%Out)
Fout.write('end\n')
Fout.write('endmodule\n')
Fout.close()
def excecuteLine(Mod, wrds, Env):
wrds = scanFunctions(wrds, Env, Mod)
if (wrds[0] == 'source'):
Fname = wrds[1]
os.system(Fname)
return
if (wrds[0] == 'new'):
newModule = wrds[1]
Env.Current = module_class.module_class(newModule)
Env.Modules[newModule] = Env.Current
return
if (wrds[0] == 'load'):
Fname = wrds[1]
Env.read_verilog_file(Fname, Env.rundir, Env)
return
if (wrds[0] == 'assign'):
Mod.add_hard_assign(wrds[1], wrds[2])
if (wrds[0] == 'add_inout'):
add_wires(Mod, 'inout', wrds[1:])
return
if (wrds[0] == 'add_input'):
add_wires(Mod, 'input', wrds[1:])
return
if (wrds[0] == 'add_output'):
add_wires(Mod, 'output', wrds[1:])
return
if (wrds[0] == 'copy_params'):
From = wrds[1]
Other = Env.Modules[From]
for Param in Other.parameters:
Mod.parameters[Param] = Other.parameters[Param]
for Param in Other.localparams:
Mod.localparams[Param] = Other.localparams[Param]
return
if (wrds[0] == 'copy_inst'):
From = wrds[1]
TypeInst = wrds[2]
if From not in Env.Modules:
Env.try_and_load_module(From, Env)
if From not in Env.Modules:
logs.log_error('failed to load "%s" module' % (From))
return
Other = Env.Modules[From]
for Inst in Other.insts:
found = False
if (Inst == TypeInst):
Type = Other.insts[Inst].Type
Mod.add_inst(Other.insts[Inst].Type, Inst)
found = True
elif (Other.insts[Inst].Type == TypeInst):
Mod.add_inst(TypeInst, Inst)
found = True
if found:
Oobj = Other.insts[Inst]
for Pin in Oobj.conns:
Sig = Oobj.conns[Pin]
if (type(Sig) is str) and (Sig in Other.nets):
_, WW = Other.nets[Sig]
if (type(WW) is tuple) and (len(WW) == 2):
Sig = '%s%s' % (Sig, module_class.pr_wid(WW))
Sup = module_class.support_set(WW[0])
for Param in Sup:
if Param in Other.parameters:
Mod.parameters[Param] = Other.parameters[
Param]
elif Param in Other.localparams:
Mod.localparams[Param] = Other.localparams[
Param]
Mod.add_conn(Inst, Pin, module_class.pr_expr(Sig))
for Param in Oobj.params:
Mod.insts[Inst].params[Param] = Oobj.params[Param]
return
if (wrds[0] == 'unconn'):
Inst = wrds[1]
if Inst not in Mod.insts:
logs.log_error('instance %s is not in module' % Inst)
return
Obj = Mod.insts[Inst]
for Pin in wrds[2:]:
if Pin in Obj.conns:
Obj.conns[Pin] = False
Env.donesx += 1
else:
Obj.conns[Pin] = False
return
if (wrds[0] == 'del_conn'):
Inst = wrds[1]
if Inst not in Mod.insts:
logs.log_error('instance %s is not in module' % Inst)
return
Obj = Mod.insts[Inst]
for Pin in wrds[2:]:
if Pin in Obj.conns:
Obj.conns.pop(Pin)
else:
logs.log_error('del_conn isnt=%s pin=%s failed' % (Inst, Pin))
return
if (wrds[0] == 'add_conn'):
Inst = wrds[1]
if Inst not in Mod.insts:
logs.log_error('instance %s is not in module' % Inst)
return
add_conns(Mod, Inst, wrds[2:], Env)
return
if (wrds[0] == 'del_inst'):
for Inst in wrds[1:]:
if Inst in Mod.insts:
Mod.insts.pop(Inst)
Env.donesx += 1
else:
logs.log_error('del instance %s is not in module' % Inst)
return
if (wrds[0] == 'del_wire'):
for Net in wrds[1:]:
if Net in Mod.nets:
Mod.nets.pop(Net)
Env.donesx += 1
else:
logs.log_error('net %s is not in module' % Net)
return
if (wrds[0] == 'add_inst'):
Type = wrds[1]
Inst = wrds[2]
Mod.add_inst(Type, Inst)
add_conns(Mod, Inst, wrds[3:], Env)
return
if (wrds[0] == 'add_param'):
Inst = wrds[1]
for PrmVal in wrds[2:]:
Prm, Val = PrmVal.split('=')
Mod.add_inst_param(Inst, Prm, Val)
return
if (wrds[0] == 'add_wire'):
Dir = wrds[1]
Wid = eval(wrds[2])
for Net in wrds[3:]:
Mod.add_sig(Net, Dir, Wid)
return
if (wrds[0] == 'rename_inst'):
Old = wrds[1]
New = wrds[2]
if Old not in Mod.insts:
logs.log_error('inst %s is not in module' % (Old))
return
Obj = Mod.insts.pop(Old)
Obj.Name = New
Mod.insts[New] = Obj
return
if (wrds[0] == 'retype_inst'):
Old = wrds[1]
Type = wrds[2]
if len(wrds) >= 4:
New = wrds[3]
else:
New = Old
if Old not in Mod.insts:
logs.log_error('inst %s / %s is not in module' % (Type, Old))
return
Obj = Mod.insts[Old]
Obj.Type = Type
Obj.Name = New
if Old != New:
Mod.insts.pop(Old)
Mod.insts[New] = Obj
Env.donesx += 1
return
if (wrds[0] == 'report_connectivity'):
report_connectivity(Mod, Env)
pairsTable(Mod)
singlesTable(Mod)
return
if (wrds[0] == 'remove_unused_wires'):
removeUnused(Mod)
return
if (wrds[0] == 'elaborateSimpleAssigns'):
elaborateSimpleAssigns(Mod)
return
if (wrds[0] == 'assign'):
treatAssigns(Env, Mod, wrds[1], wrds[2])
return
if (wrds[0] == 'save'):
Fname = wrds[1]
execute_line('dump_verilog %s' % Fname, Env)
return
if wrds[0].startswith('remove_gen'):
Mod.generates = []
return
if wrds[0] == 'new_hierarchy':
Mod.prepareNetTable()
Mod.mergeNetTableBusses()
Name = wrds[1]
New = module_class.module_class(Name)
Env.Modules[Name] = New
Insts = wrds[2:]
for Inst in wrds[2:]:
if Inst in Mod.insts:
Obj = Mod.insts[Inst]
New.insts[Inst] = Obj
Mod.insts.pop(Inst)
Nets = list(Mod.nets.keys())
Mod.insts[Name] = module_class.instance_class(Name, Name)
for Net in Nets:
if Net in Mod.netTable:
List = Mod.netTable[Net]
In, Out = False, False
for (Pin, Inst, Type) in List:
if Inst in Insts: In = True
if Inst in Mod.insts: Out = True
if In and not Out:
New.nets[Net] = Mod.nets[Net]
Mod.nets.pop(Net)
elif In and Out:
Dir, Wid = Mod.nets[Net]
New.nets[Net] = 'inout', Wid
Mod.insts[Name].conns[Net] = Net
Fout = open('%s.v' % Name, 'w')
New.dump_verilog(Fout)
Fout.close()
logs.log_error('bad command line %s' % ' '.join(wrds))
def dump_instance(Mod,Simple=False):
Name = Mod.Module
Fout = open('%s.inst'%(Name),'w')
if not Simple:
Fout.write('module tb;\n')
Fout.write('reg [31:0] cycles; initial cycles=0;\n')
Fout.write('reg [31:0] errors; initial errors=0;\n')
Fout.write('reg [31:0] wrongs; initial wrongs=0;\n')
Fout.write('reg [31:0] panics; initial panics=0;\n')
Fout.write('reg [31:0] corrects; initial corrects=0;\n')
Fout.write('reg [31:0] marker; initial marker=0;\n')
for Param in Mod.parameters:
Val = Mod.parameters[Param]
Fout.write('parameter %s = %s;\n'%(Param,pr_expr(Val)))
Regs=''
Sigs = Mod.nets.keys()
Sigs.sort()
for Sig in Sigs:
DirHL = Mod.nets[Sig]
Dir1 = DirHL[0]
if Simple:
Fout.write('wire %s %s;\n'%(wids(DirHL[1]),Sig))
elif ('input' in Dir1):
Fout.write('reg %s %s;\n'%(wids(DirHL[1]),Sig))
Regs +=' %s = 0;\n'%(Sig)
elif ('output' in Dir1):
Fout.write('wire %s %s;\n'%(wids(DirHL[1]),Sig))
elif ('inout' in Dir1):
Fout.write('inout_driver drv_%s(.io(%s),.dflt(1\'b0));\n'%(Sig,Sig))
if not Simple:
Fout.write(String1)
Fout.write(Regs)
Fout.write(' #100;\n rst_n=1;\nend\n')
Fout.write('%s dut (\n'%(Name))
Pref=' '
for Sig in Sigs:
DirHL = Mod.nets[Sig]
Dir1 = string.split(DirHL[0])[0]
if (Dir1=='output')or(Dir1=='inout')or(Dir1=='input'):
Wids = wids(DirHL[1])
if '][' in Wids: Wids=''
Fout.write(' %s.%s(%s%s)\n'%(Pref,Sig,Sig,Wids))
Pref=','
Fout.write(');\n')
if not Simple:
Fout.write(PLUSARG)
Fout.write('endmodule\n')
Fout.write(INOUT_DRIVER)
Fout.close()
Fout = open('%s.inst.py'%(Name),'w')
Fout.write(String2)
Fout.write('def cucu():\n')
for Sig in Sigs:
DirHL = Mod.nets[Sig]
Dir1 = string.split(DirHL[0])[0]
if (Dir1=='input')and(Sig not in ['clk','rst_n']):
Fout.write(" veri.force('tb.%s','0')\n"%(Sig))
for Sig in Sigs:
DirHL = Mod.nets[Sig]
Dir1 = string.split(DirHL[0])[0]
if (Dir1=='output'):
Fout.write(" %s = logs.peek('tb.%s')\n"%(Sig,Sig))
Fout.close()
