def files(bot, update):
s = update.message
msg.echo(update)
if utils.isAdmin(s.from_user.id):
bot.send_message(chat_id=s.chat_id, text=msg.filesText())
else:
bot.send_message(chat_id=s.chat_id, text=msg.notAnAdmin)
def start(bot, update):
""" Envia el mensaje de bienvenida. """
s = update.message
msg.echo(update)
bot.send_message(chat_id=s.chat_id,
text=msg.infoStartBot,
reply_markup=butt.menu())
def help(bot, update):
""" Envia el mensaje de ayuda. """
s = update.message
msg.echo(update)
if utils.isAdmin(s.from_user.id):
bot.send_message(chat_id=s.chat_id, text=msg.infoAdmins)
else:
bot.send_message(chat_id=s.chat_id, text=msg.infoHelp)
def unknown(bot, update):
""" Recibe cualquier comando no reconocido e informa de que no existe. """
s = update.message
msg.echo(update)
bot.send_message(chat_id=s.chat_id,
text=msg.infoUnkown,
reply_markup=butt.menu())
print(msg.unknown)
def contribute(bot, update):
s = update.message
if not utils.isAdmin(s.from_user.id):
update.message.reply_text(msg.reportNotAdmin)
msg.echo(update)
else:
update.message.reply_text(msg.whatFor, reply_markup=butt.links())
msg.echo(update)
return CHOOSING
def check_address_length(self):
p = self.popen("uname -a")
p = p.readlines()
if not len(p):
p.echo("Checking address length failed")
return None
elif "i686" in p[0]:
return 32
elif "x86_64" in p[0]:
return 64
else:
return None
def check_address_length(self):
p = self.popen("uname -a")
p = p.readlines()
if not len(p):
p.echo("Checking address length failed")
return None
elif "i686" in p[0]:
return 32
elif "x86_64" in p[0]:
return 64
else:
return None
def generate_isim_makefile(self):
# p.info("Generating makefile for simulation.")
p.info("Generating ISE Simulation (ISim) makefile for simulation.")
solver = DependencySolver()
pool = self.modules_pool
if not pool.is_everything_fetched():
p.echo("A module remains unfetched. "
"Fetching must be done prior to makefile generation. Try issuing \"hdlmake2 --fetch\"")
p.echo(str([str(m) for m in self.modules_pool.modules if not m.isfetched]))
quit()
top_module = pool.get_top_module()
flist = pool.build_global_file_list();
flist_sorted = solver.solve(flist);
self.make_writer.generate_isim_makefile(flist_sorted, top_module)
def generate_ise_project(self):
p.info("Generating/updating ISE project")
if self.__is_xilinx_screwed():
p.error("Xilinx environment variable is unset or is wrong.\n"
"Cannot generate ise project")
quit()
if not self.modules_pool.is_everything_fetched():
p.echo("A module remains unfetched. Fetching must be done prior to makefile generation")
p.echo(str([str(m) for m in self.modules_pool if not m.isfetched]))
quit()
ise = self.__check_ise_version()
if os.path.exists(self.top_module.syn_project):
self.__update_existing_ise_project(ise=ise)
else:
self.__create_new_ise_project(ise=ise)
def generate_ise_project(self):
p.info("Generating/updating ISE project")
if self.__is_xilinx_screwed():
p.error("Xilinx environment variable is unset or is wrong.\n"
"Cannot generate ise project")
quit()
if not self.modules_pool.is_everything_fetched():
p.echo(
"A module remains unfetched. Fetching must be done prior to makefile generation"
)
p.echo(str([str(m) for m in self.modules_pool if not m.isfetched]))
quit()
ise = self.__check_ise_version()
if os.path.exists(self.top_module.syn_project):
self.__update_existing_ise_project(ise=ise)
else:
self.__create_new_ise_project(ise=ise)
def generate_vsim_makefile(self):
# p.info("Generating makefile for simulation.")
p.info("Generating ModelSim makefile for simulation.")
solver = DependencySolver()
pool = self.modules_pool
if not pool.is_everything_fetched():
p.echo("A module remains unfetched. "
"Fetching must be done prior to makefile generation")
p.echo(
str([
str(m) for m in self.modules_pool.modules
if not m.isfetched
]))
quit()
top_module = pool.get_top_module()
flist = pool.build_global_file_list()
flist_sorted = solver.solve(flist)
#self.make_writer.generate_vsim_makefile(flist_sorted, top_module)
self.make_writer.generate_vsim_makefile(flist_sorted, top_module)
def merge_cores(self):
from srcfile import VerilogFile, VHDLFile, SVFile, NGCFile
from vlog_parser import VerilogPreprocessor
solver = DependencySolver()
pool = self.modules_pool
if not pool.is_everything_fetched():
p.echo(
"A module remains unfetched. Fetching must be done prior to makefile generation"
)
p.echo(
str([
str(m) for m in self.modules_pool.modules
if not m.isfetched
]))
quit()
flist = pool.build_global_file_list()
flist_sorted = solver.solve(flist)
# if not os.path.exists(self.options.merge_cores):
# os.makedirs(self.options.merge_cores)
base = self.options.merge_cores
f_out = open(base + ".vhd", "w")
f_out.write("\n\n\n\n")
f_out.write(
"------------------------------ WARNING -------------------------------\n"
)
f_out.write(
"-- This code has been generated by hdlmake --merge-cores option --\n"
)
f_out.write(
"-- It is provided for your convenience, to spare you from adding --\n"
)
f_out.write(
"-- lots of individual source files to ISE/Modelsim/Quartus projects --\n"
)
f_out.write(
"-- mainly for Windows users. Please DO NOT MODIFY this file. If you --\n"
)
f_out.write(
"-- need to change something inside, edit the original source file --\n"
)
f_out.write(
"-- and re-genrate the merged version! --\n"
)
f_out.write(
"----------------------------------------------------------------------\n"
)
f_out.write("\n\n\n\n")
for vhdl in flist_sorted.filter(VHDLFile):
f_out.write("\n\n--- File: %s ----\n\n" % vhdl.rel_path())
f_out.write(open(vhdl.rel_path(), "r").read() + "\n\n")
#print("VHDL: %s" % vhdl.rel_path())
f_out.close()
f_out = open(base + ".v", "w")
f_out.write("\n\n\n\n")
f_out.write(
"////////////////////////////// WARNING ///////////////////////////////\n"
)
f_out.write(
"// This code has been generated by hdlmake --merge-cores option //\n"
)
f_out.write(
"// It is provided for your convenience, to spare you from adding //\n"
)
f_out.write(
"// lots of individual source files to ISE/Modelsim/Quartus projects //\n"
)
f_out.write(
"// mainly for Windows users. Please DO NOT MODIFY this file. If you //\n"
)
f_out.write(
"// need to change something inside, edit the original source file //\n"
)
f_out.write(
"// and re-genrate the merged version! //\n"
)
f_out.write(
"//////////////////////////////////////////////////////////////////////\n"
)
f_out.write("\n\n\n\n")
for vlog in flist_sorted.filter(VerilogFile):
f_out.write("\n\n// File: %s \n\n" % vlog.rel_path())
vpp = VerilogPreprocessor()
vpp.add_path(vlog.dirname)
f_out.write(vpp.preprocess(vlog.rel_path()))
f_out.close()
for ngc in flist_sorted.filter(NGCFile):
import shutil
print("NGC:%s " % ngc.rel_path())
shutil.copy(ngc.rel_path(), self.options.merge_cores + "/")
def parse_manifest(self):
if self.isparsed == True or self.isfetched == False:
return
if self.manifest == None:
self.manifest = self.__search_for_manifest()
if self.path == None:
raise RuntimeError()
manifest_parser = ManifestParser()
# For non-top modules
if(self.parent != None):
manifest_parser.add_arbitrary_code("target=\""+str(global_mod.top_module.target)+"\"")
manifest_parser.add_arbitrary_code("action=\""+str(global_mod.top_module.action)+"\"")
# syn_device and sim_tool will be set for non-top modules
manifest_parser.add_arbitrary_code("syn_device=\""+str(global_mod.top_module.syn_device)+"\"")
manifest_parser.add_arbitrary_code("__manifest=\""+self.path+"\"")
manifest_parser.add_arbitrary_code(global_mod.options.arbitrary_code)
if self.manifest == None:
p.vprint("No manifest found in module "+str(self))
else:
manifest_parser.add_manifest(self.manifest)
p.vprint("Parsing manifest file: " + str(self.manifest))
opt_map = None
try:
opt_map = manifest_parser.parse()
except NameError as ne:
p.echo("Error while parsing {0}:\n{1}: {2}.".format(self.manifest, type(ne), ne))
quit()
if(opt_map["fetchto"] != None):
fetchto = path_mod.rel2abs(opt_map["fetchto"], self.path)
self.fetchto = fetchto
else:
fetchto = self.fetchto
if self.ise == None:
self.ise = "13.1"
if "local" in opt_map["modules"]:
local_paths = self.__make_list(opt_map["modules"]["local"])
local_mods = []
for path in local_paths:
if path_mod.is_abs_path(path):
p.error("Found an absolute path (" + path + ") in a manifest")
p.rawprint("(" + self.path + ")")
quit()
path = path_mod.rel2abs(path, self.path)
local_mods.append(self.pool.new_module(parent=self, url=path, source="local", fetchto=fetchto))
self.local = local_mods
else:
self.local = []
self.vmap_opt = opt_map["vmap_opt"]
self.vcom_opt = opt_map["vcom_opt"]
self.vsim_opt = opt_map["vsim_opt"]
self.vlog_opt = opt_map["vlog_opt"]
#if self.vlog_opt == "":
# self.vlog_opt = global_mod.top_module.vlog_opt
#if self.vcom_opt == "":
# self.vcom_opt = global_mod.top_module.vcom_opt
#if self.vsim_opt == "":
# self.vsim_opt = global_mod.top_module.vsim_opt
# if self.vmap_opt == "":
# self.vmap_opt = global_mod.top_module.vmap_opt
self.library = opt_map["library"]
self.include_dirs = []
if opt_map["include_dirs"] != None:
if isinstance(opt_map["include_dirs"], basestring):
self.include_dirs.append(opt_map["include_dirs"])
else:
self.include_dirs.extend(opt_map["include_dirs"])
for dir in self.include_dirs:
if path_mod.is_abs_path(dir):
p.warning(self.path + " contains absolute path to an include directory: " +
dir)
if not os.path.exists(dir):
p.warning(self.path + " has an unexisting include directory: " + dir)
if opt_map["files"] == []:
self.files = SourceFileSet()
else:
opt_map["files"] = self.__make_list(opt_map["files"])
paths = []
for path in opt_map["files"]:
if not path_mod.is_abs_path(path):
path = path_mod.rel2abs(path, self.path)
paths.append(path)
else:
p.warning(path + " is an absolute path. Omitting.")
if not os.path.exists(path):
p.error("File listed in " + self.manifest.path + " doesn't exist: "
+ path +".\nExiting.")
quit()
from srcfile import VerilogFile, VHDLFile
self.files = self.__create_file_list_from_paths(paths=paths);
for f in self.files:
if isinstance(f, VerilogFile):
f.vsim_opt = self.vsim_opt
elif isinstance(f, VHDLFile):
f.vcom_opt = self.vcom_opt
if "svn" in opt_map["modules"]:
opt_map["modules"]["svn"] = self.__make_list(opt_map["modules"]["svn"])
svn_mods = []
for url in opt_map["modules"]["svn"]:
svn_mods.append(self.pool.new_module(parent=self, url=url, source="svn", fetchto=fetchto))
self.svn = svn_mods
else:
self.svn = []
if "git" in opt_map["modules"]:
opt_map["modules"]["git"] = self.__make_list(opt_map["modules"]["git"])
git_mods = []
for url in opt_map["modules"]["git"]:
git_mods.append(self.pool.new_module(parent=self, url=url, source="git", fetchto=fetchto))
self.git = git_mods
else:
self.git = []
self.target = opt_map["target"]
self.action = opt_map["action"]
if opt_map["syn_name"] == None and opt_map["syn_project"] != None:
self.syn_name = opt_map["syn_project"][:-5] #cut out .xise from the end
else:
self.syn_name = opt_map["syn_name"]
self.syn_device = opt_map["syn_device"];
self.syn_grade = opt_map["syn_grade"];
self.syn_package= opt_map["syn_package"];
self.syn_project = opt_map["syn_project"];
self.syn_top = opt_map["syn_top"];
self.isparsed = True
for m in self.submodules():
m.parse_manifest()
def merge_cores(self):
from srcfile import VerilogFile, VHDLFile, SVFile, NGCFile
from vlog_parser import VerilogPreprocessor
solver = DependencySolver()
pool = self.modules_pool
if not pool.is_everything_fetched():
p.echo("A module remains unfetched. Fetching must be done prior to makefile generation")
p.echo(str([str(m) for m in self.modules_pool.modules if not m.isfetched]))
quit()
flist = pool.build_global_file_list();
flist_sorted = solver.solve(flist);
# if not os.path.exists(self.options.merge_cores):
# os.makedirs(self.options.merge_cores)
base = self.options.merge_cores
f_out = open(base+".vhd", "w")
f_out.write("\n\n\n\n");
f_out.write("------------------------------ WARNING -------------------------------\n");
f_out.write("-- This code has been generated by hdlmake --merge-cores option --\n");
f_out.write("-- It is provided for your convenience, to spare you from adding --\n");
f_out.write("-- lots of individual source files to ISE/Modelsim/Quartus projects --\n");
f_out.write("-- mainly for Windows users. Please DO NOT MODIFY this file. If you --\n");
f_out.write("-- need to change something inside, edit the original source file --\n");
f_out.write("-- and re-genrate the merged version! --\n");
f_out.write("----------------------------------------------------------------------\n");
f_out.write("\n\n\n\n");
for vhdl in flist_sorted.filter(VHDLFile):
f_out.write("\n\n--- File: %s ----\n\n" % vhdl.rel_path())
f_out.write(open(vhdl.rel_path(),"r").read()+"\n\n")
#print("VHDL: %s" % vhdl.rel_path())
f_out.close()
f_out = open(base+".v", "w")
f_out.write("\n\n\n\n");
f_out.write("////////////////////////////// WARNING ///////////////////////////////\n");
f_out.write("// This code has been generated by hdlmake --merge-cores option //\n");
f_out.write("// It is provided for your convenience, to spare you from adding //\n");
f_out.write("// lots of individual source files to ISE/Modelsim/Quartus projects //\n");
f_out.write("// mainly for Windows users. Please DO NOT MODIFY this file. If you //\n");
f_out.write("// need to change something inside, edit the original source file //\n");
f_out.write("// and re-genrate the merged version! //\n");
f_out.write("//////////////////////////////////////////////////////////////////////\n");
f_out.write("\n\n\n\n");
for vlog in flist_sorted.filter(VerilogFile):
f_out.write("\n\n// File: %s \n\n" % vlog.rel_path())
vpp = VerilogPreprocessor()
vpp.add_path(vlog.dirname)
f_out.write(vpp.preprocess(vlog.rel_path()))
f_out.close()
for ngc in flist_sorted.filter(NGCFile):
import shutil
print("NGC:%s " % ngc.rel_path())
shutil.copy(ngc.rel_path(), self.options.merge_cores+"/")
def __check(self):
if not self.__data_given():
p.echo("Error: no data for connection given")
quit()
def __check(self):
if not self.__data_given():
p.echo("Error: no data for connection given")
quit()
def parse_manifest(self):
if self.isparsed == True or self.isfetched == False:
return
if self.manifest == None:
self.manifest = self.__search_for_manifest()
if self.path == None:
raise RuntimeError()
manifest_parser = ManifestParser()
# For non-top modules
if (self.parent != None):
manifest_parser.add_arbitrary_code(
"target=\"" + str(global_mod.top_module.target) + "\"")
manifest_parser.add_arbitrary_code(
"action=\"" + str(global_mod.top_module.action) + "\"")
# syn_device and sim_tool will be set for non-top modules
manifest_parser.add_arbitrary_code(
"syn_device=\"" + str(global_mod.top_module.syn_device) + "\"")
manifest_parser.add_arbitrary_code("__manifest=\"" + self.path + "\"")
manifest_parser.add_arbitrary_code(global_mod.options.arbitrary_code)
if self.manifest == None:
p.vprint("No manifest found in module " + str(self))
else:
manifest_parser.add_manifest(self.manifest)
p.vprint("Parsing manifest file: " + str(self.manifest))
opt_map = None
try:
opt_map = manifest_parser.parse()
except NameError as ne:
p.echo("Error while parsing {0}:\n{1}: {2}.".format(
self.manifest, type(ne), ne))
quit()
if (opt_map["fetchto"] != None):
fetchto = path_mod.rel2abs(opt_map["fetchto"], self.path)
self.fetchto = fetchto
else:
fetchto = self.fetchto
if self.ise == None:
self.ise = "13.1"
if "local" in opt_map["modules"]:
local_paths = self.__make_list(opt_map["modules"]["local"])
local_mods = []
for path in local_paths:
if path_mod.is_abs_path(path):
p.error("Found an absolute path (" + path +
") in a manifest")
p.rawprint("(" + self.path + ")")
quit()
path = path_mod.rel2abs(path, self.path)
local_mods.append(
self.pool.new_module(parent=self,
url=path,
source="local",
fetchto=fetchto))
self.local = local_mods
else:
self.local = []
self.vmap_opt = opt_map["vmap_opt"]
self.vcom_opt = opt_map["vcom_opt"]
self.vsim_opt = opt_map["vsim_opt"]
self.vlog_opt = opt_map["vlog_opt"]
#if self.vlog_opt == "":
# self.vlog_opt = global_mod.top_module.vlog_opt
#if self.vcom_opt == "":
# self.vcom_opt = global_mod.top_module.vcom_opt
#if self.vsim_opt == "":
# self.vsim_opt = global_mod.top_module.vsim_opt
# if self.vmap_opt == "":
# self.vmap_opt = global_mod.top_module.vmap_opt
self.library = opt_map["library"]
self.include_dirs = []
if opt_map["include_dirs"] != None:
if isinstance(opt_map["include_dirs"], basestring):
self.include_dirs.append(opt_map["include_dirs"])
else:
self.include_dirs.extend(opt_map["include_dirs"])
for dir in self.include_dirs:
if path_mod.is_abs_path(dir):
p.warning(self.path +
" contains absolute path to an include directory: " +
dir)
if not os.path.exists(dir):
p.warning(self.path +
" has an unexisting include directory: " + dir)
if opt_map["files"] == []:
self.files = SourceFileSet()
else:
opt_map["files"] = self.__make_list(opt_map["files"])
paths = []
for path in opt_map["files"]:
if not path_mod.is_abs_path(path):
path = path_mod.rel2abs(path, self.path)
paths.append(path)
else:
p.warning(path + " is an absolute path. Omitting.")
if not os.path.exists(path):
p.error("File listed in " + self.manifest.path +
" doesn't exist: " + path + ".\nExiting.")
quit()
from srcfile import VerilogFile, VHDLFile
self.files = self.__create_file_list_from_paths(paths=paths)
for f in self.files:
if isinstance(f, VerilogFile):
f.vsim_opt = self.vsim_opt
elif isinstance(f, VHDLFile):
f.vcom_opt = self.vcom_opt
if "svn" in opt_map["modules"]:
opt_map["modules"]["svn"] = self.__make_list(
opt_map["modules"]["svn"])
svn_mods = []
for url in opt_map["modules"]["svn"]:
svn_mods.append(
self.pool.new_module(parent=self,
url=url,
source="svn",
fetchto=fetchto))
self.svn = svn_mods
else:
self.svn = []
if "git" in opt_map["modules"]:
opt_map["modules"]["git"] = self.__make_list(
opt_map["modules"]["git"])
git_mods = []
for url in opt_map["modules"]["git"]:
git_mods.append(
self.pool.new_module(parent=self,
url=url,
source="git",
fetchto=fetchto))
self.git = git_mods
else:
self.git = []
self.target = opt_map["target"]
self.action = opt_map["action"]
if opt_map["syn_name"] == None and opt_map["syn_project"] != None:
self.syn_name = opt_map[
"syn_project"][:-5] #cut out .xise from the end
else:
self.syn_name = opt_map["syn_name"]
self.syn_device = opt_map["syn_device"]
self.syn_grade = opt_map["syn_grade"]
self.syn_package = opt_map["syn_package"]
self.syn_project = opt_map["syn_project"]
self.syn_top = opt_map["syn_top"]
self.isparsed = True
for m in self.submodules():
m.parse_manifest()
def main():
usage = "usage: %prog [options]\n"
usage += "type %prog --help to get help message"
parser = optparse.OptionParser(usage=usage)
parser.add_option("--manifest-help", action="store_true",
dest="manifest_help", help="print manifest file variables description")
parser.add_option("--make-vsim", dest="make_vsim", action="store_true",
default=None, help="generate a ModelSim simulation Makefile")
parser.add_option("--make-isim", dest="make_isim", action="store_true",
default=None, help="generate a ISE Simulation (ISim) simulation Makefile")
parser.add_option("--make-fetch", dest="make_fetch", action="store_true",
default=None, help="generate a makefile for modules' fetching")
parser.add_option("--make-ise", dest="make_ise", action="store_true",
default=None, help="generate a makefile for local ISE synthesis")
parser.add_option("--make-remote", dest="make_remote", action="store_true",
default=None, help="generate a makefile for remote synthesis")
parser.add_option("-f", "--fetch", action="store_true", dest="fetch",
default=None, help="fetch and/or update remote modules listed in Manifest")
parser.add_option("--clean", action="store_true", dest="clean",
default=None, help="remove all modules fetched for this one")
parser.add_option("--list", action="store_true", dest="list",
default=None, help="List all modules together with their files")
parser.add_option("--list-files", action="store_true", dest="list_files",
default=None, help="List all files in a from of a space-separated string")
parser.add_option("--merge-cores=name", default=None, dest="merge_cores",
help="Merges entire synthesizable content of an project into a pair of VHDL/Verilog files")
parser.add_option("--ise-proj", action="store_true", dest="ise_proj",
default=None, help="create/update an ise project including list of project"
"files")
parser.add_option("--quartus-proj", action="store_true", dest="quartus_proj",
default=None, help="create/update a quartus project including list of project"
"files")
parser.add_option("-l", "--synthesize-locally", dest="local",
default=None, action="store_true", help="perform a local synthesis")
parser.add_option("-r", "--synthesize-remotelly", dest="remote",
default=None, action="store_true", help="perform a remote synthesis")
parser.add_option("--synth-server", dest="synth_server",
default=None, help="use given SERVER for remote synthesis",
metavar="SERVER")
parser.add_option("--synth-user", dest="synth_user",
default=None, help="use given USER for remote synthesis", metavar="USER")
parser.add_option("--force-ise", dest="force_ise",
default=None, type=float, help="Force given ISE version to be used in"
" synthesis,use 0 for current version", metavar="ISE")
parser.add_option("--py", dest="arbitrary_code",
default="", help="add arbitrary code to all manifests' evaluation")
parser.add_option("-v", "--verbose", dest="verbose", action="store_true",
default="false", help="verbose mode")
parser.add_option("--version", dest="print_version", action="store_true",
default="false", help="print version id of this Hdlmake build")
(options, _) = parser.parse_args()
global_mod.options = options
#HANDLE PROJECT INDEPENDENT OPTIONS
if options.manifest_help == True:
from manifest_parser import ManifestParser
ManifestParser().help()
quit()
if options.print_version == True:
p.print_version()
quit()
# Check later if a simulation tool should have been specified
if options.make_isim == True:
global_mod.sim_tool = "isim"
elif options.make_vsim == True:
global_mod.sim_tool = "vsim"
p.info("Simulation tool: " + str(global_mod.sim_tool))
p.vprint("LoadTopManifest")
pool = ModulePool()
pool.new_module(parent=None, url=os.getcwd(), source="local", fetchto=".")
if pool.get_top_module().manifest == None:
p.rawprint("No manifest found. At least an empty one is needed")
p.rawprint("To see some help, type hdlmake --help")
quit()
global_mod.top_module = pool.get_top_module()
global_mod.global_target = global_mod.top_module.target
ssh = Connection(ssh_user=options.synth_user,
ssh_server=options.synth_server)
from hdlmake_kernel import HdlmakeKernel
kernel = HdlmakeKernel(modules_pool=pool, connection=ssh, options=options)
options_kernel_mapping = {
"fetch" : "fetch",
"make_vsim" : "generate_vsim_makefile",
"make_isim" : "generate_isim_makefile",
"ise_proj" : "generate_ise_project",
"quartus_proj" : "generate_quartus_project",
"local" : "run_local_synthesis",
"remote": "run_remote_synthesis",
"make_fetch": "generate_fetch_makefile",
"make_ise" : "generate_ise_makefile",
"make_remote" : "generate_remote_synthesis_makefile",
"list" : "list_modules",
"clean" : "clean_modules",
"merge_cores" : "merge_cores"
}
sth_chosen = False
import traceback
for option, function in options_kernel_mapping.items():
try:
is_set = getattr(options, option)
if is_set:
sth_chosen = True
getattr(kernel, function)()
except Exception, unknown_error :
p.echo("Oooops! We've got an error. Here is the appropriate info:\n")
p.print_version()
print(unknown_error)
traceback.print_exc()
def main():
usage = "usage: %prog [options]\n"
usage += "type %prog --help to get help message"
parser = optparse.OptionParser(usage=usage)
parser.add_option("--manifest-help",
action="store_true",
dest="manifest_help",
help="print manifest file variables description")
parser.add_option("--make-vsim",
dest="make_vsim",
action="store_true",
default=None,
help="generate a ModelSim simulation Makefile")
parser.add_option(
"--make-isim",
dest="make_isim",
action="store_true",
default=None,
help="generate a ISE Simulation (ISim) simulation Makefile")
parser.add_option("--make-fetch",
dest="make_fetch",
action="store_true",
default=None,
help="generate a makefile for modules' fetching")
parser.add_option("--make-ise",
dest="make_ise",
action="store_true",
default=None,
help="generate a makefile for local ISE synthesis")
parser.add_option("--make-remote",
dest="make_remote",
action="store_true",
default=None,
help="generate a makefile for remote synthesis")
parser.add_option(
"-f",
"--fetch",
action="store_true",
dest="fetch",
default=None,
help="fetch and/or update remote modules listed in Manifest")
parser.add_option("--clean",
action="store_true",
dest="clean",
default=None,
help="remove all modules fetched for this one")
parser.add_option("--list",
action="store_true",
dest="list",
default=None,
help="List all modules together with their files")
parser.add_option(
"--list-files",
action="store_true",
dest="list_files",
default=None,
help="List all files in a from of a space-separated string")
parser.add_option(
"--merge-cores=name",
default=None,
dest="merge_cores",
help=
"Merges entire synthesizable content of an project into a pair of VHDL/Verilog files"
)
parser.add_option(
"--ise-proj",
action="store_true",
dest="ise_proj",
default=None,
help="create/update an ise project including list of project"
"files")
parser.add_option(
"--quartus-proj",
action="store_true",
dest="quartus_proj",
default=None,
help="create/update a quartus project including list of project"
"files")
parser.add_option("-l",
"--synthesize-locally",
dest="local",
default=None,
action="store_true",
help="perform a local synthesis")
parser.add_option("-r",
"--synthesize-remotelly",
dest="remote",
default=None,
action="store_true",
help="perform a remote synthesis")
parser.add_option("--synth-server",
dest="synth_server",
default=None,
help="use given SERVER for remote synthesis",
metavar="SERVER")
parser.add_option("--synth-user",
dest="synth_user",
default=None,
help="use given USER for remote synthesis",
metavar="USER")
parser.add_option("--force-ise",
dest="force_ise",
default=None,
type=float,
help="Force given ISE version to be used in"
" synthesis,use 0 for current version",
metavar="ISE")
parser.add_option("--py",
dest="arbitrary_code",
default="",
help="add arbitrary code to all manifests' evaluation")
parser.add_option("-v",
"--verbose",
dest="verbose",
action="store_true",
default="false",
help="verbose mode")
parser.add_option("--version",
dest="print_version",
action="store_true",
default="false",
help="print version id of this Hdlmake build")
(options, _) = parser.parse_args()
global_mod.options = options
#HANDLE PROJECT INDEPENDENT OPTIONS
if options.manifest_help == True:
from manifest_parser import ManifestParser
ManifestParser().help()
quit()
if options.print_version == True:
p.print_version()
quit()
# Check later if a simulation tool should have been specified
if options.make_isim == True:
global_mod.sim_tool = "isim"
elif options.make_vsim == True:
global_mod.sim_tool = "vsim"
p.info("Simulation tool: " + str(global_mod.sim_tool))
p.vprint("LoadTopManifest")
pool = ModulePool()
pool.new_module(parent=None, url=os.getcwd(), source="local", fetchto=".")
if pool.get_top_module().manifest == None:
p.rawprint("No manifest found. At least an empty one is needed")
p.rawprint("To see some help, type hdlmake --help")
quit()
global_mod.top_module = pool.get_top_module()
global_mod.global_target = global_mod.top_module.target
ssh = Connection(ssh_user=options.synth_user,
ssh_server=options.synth_server)
from hdlmake_kernel import HdlmakeKernel
kernel = HdlmakeKernel(modules_pool=pool, connection=ssh, options=options)
options_kernel_mapping = {
"fetch": "fetch",
"make_vsim": "generate_vsim_makefile",
"make_isim": "generate_isim_makefile",
"ise_proj": "generate_ise_project",
"quartus_proj": "generate_quartus_project",
"local": "run_local_synthesis",
"remote": "run_remote_synthesis",
"make_fetch": "generate_fetch_makefile",
"make_ise": "generate_ise_makefile",
"make_remote": "generate_remote_synthesis_makefile",
"list": "list_modules",
"clean": "clean_modules",
"merge_cores": "merge_cores"
}
sth_chosen = False
import traceback
for option, function in options_kernel_mapping.items():
try:
is_set = getattr(options, option)
if is_set:
sth_chosen = True
getattr(kernel, function)()
except Exception, unknown_error:
p.echo(
"Oooops! We've got an error. Here is the appropriate info:\n")
p.print_version()
print(unknown_error)
traceback.print_exc()