def qdrCal(self):
# Calibrates the QDRs. Run after writing to QDR.
self.fpga.write_int(
self.regs[np.where(self.regs == 'dac_reset_reg')[0][0]][1], 1)
print 'DAC on'
bFailHard = False
calVerbosity = 1
qdrMemName = self.regs[np.where(self.regs == 'qdr0_reg')[0][0]][1]
qdrNames = [
self.regs[np.where(self.regs == 'qdr0_reg')[0][0]][1],
self.regs[np.where(self.regs == 'qdr1_reg')[0][0]][1]
]
print 'Fpga Clock Rate =', self.fpga.estimate_fpga_clock()
self.fpga.get_system_information()
results = {}
for qdr in self.fpga.qdrs:
print qdr
mqdr = myQdr.from_qdr(qdr)
results[qdr.name] = mqdr.qdr_cal2(fail_hard=bFailHard)
print 'qdr cal results:', results
for qdrName in ['qdr0', 'qdr1']:
if not results[qdr.name]:
print 'Calibration Failed'
return -1
print '\n************ QDR Calibrated ************'
return 0
def qdrCal(self):
# Calibrates the QDRs. Run after writing to QDR.
self.fpga.write_int('dac_reset',1)
bQdrCal = True
bQdrCal2 = True
bFailHard = False
calVerbosity = 1
qdrMemName = 'qdr0_memory'
qdrNames = ['qdr0_memory','qdr1_memory']
print 'Fpga Clock Rate =',self.fpga.estimate_fpga_clock()
if bQdrCal:
self.fpga.get_system_information()
results = {}
for qdr in self.fpga.qdrs:
print qdr
if bQdrCal2:
mqdr = myQdr.from_qdr(qdr)
results[qdr.name] = mqdr.qdr_cal2(fail_hard=bFailHard,verbosity=calVerbosity)
else:
results[qdr.name] = qdr.qdr_cal(fail_hard=bFailHard,verbosity=calVerbosity)
print 'qdr cal results:',results
for qdrName in ['qdr0','qdr1']:
if not results[qdr.name]:
print 'Calibration Failed'
break
def qdrCal(self):
# Calibrates the QDRs. Run after writing to QDR.
self.fpga.write_int('dac_reset', 1)
bQdrCal = True
bQdrCal2 = True
bFailHard = False
calVerbosity = 1
qdrMemName = 'qdr0_memory'
qdrNames = ['qdr0_memory', 'qdr1_memory']
print 'Fpga Clock Rate =', self.fpga.estimate_fpga_clock()
if bQdrCal:
self.fpga.get_system_information()
results = {}
for qdr in self.fpga.qdrs:
print qdr
if bQdrCal2:
mqdr = myQdr.from_qdr(qdr)
results[qdr.name] = mqdr.qdr_cal2(fail_hard=bFailHard,
verbosity=calVerbosity)
else:
results[qdr.name] = qdr.qdr_cal(fail_hard=bFailHard,
verbosity=calVerbosity)
print 'qdr cal results:', results
for qdrName in ['qdr0', 'qdr1']:
if not results[qdr.name]:
print 'Calibration Failed'
break
def calQDR(self):
bQdrFlip = True
calVerbosity = 0
bFailHard = False
#self.roachController.fpga.get_system_information()
results = {}
for iQdr, qdr in enumerate(self.roachController.fpga.qdrs):
mqdr = myQdr.from_qdr(qdr)
print qdr.name
results[qdr.name] = mqdr.qdr_cal2(fail_hard=bFailHard,
verbosity=calVerbosity)
print 'Qdr cal results:', results
for qdrName in results.keys():
if not results[qdrName]:
raise ValueError
return True
def qdrCal():
time.sleep(2)
fpga = casperfpga.katcp_fpga.KatcpFpga("192.168.40.89",timeout=120.)
bFailHard = False
calVerbosity = 1
qdrMemName = 'qdr0_memory'
qdrNames = ['qdr0_memory','qdr1_memory']
print 'Fpga Clock Rate =',fpga.estimate_fpga_clock()
fpga.get_system_information()
results = {}
for qdr in fpga.qdrs:
print qdr
mqdr = myQdr.from_qdr(qdr)
results[qdr.name] = mqdr.qdr_cal2(fail_hard=bFailHard,verbosity=calVerbosity)
print 'qdr cal results:',results
for qdrName in ['qdr0','qdr1']:
if not results[qdr.name]:
print 'Calibration Failed'
break
time.sleep(1)
return
def qdrCal():
time.sleep(2)
fpga = casperfpga.katcp_fpga.KatcpFpga("192.168.40.89", timeout=120.)
bFailHard = False
calVerbosity = 1
qdrMemName = 'qdr0_memory'
qdrNames = ['qdr0_memory', 'qdr1_memory']
print 'Fpga Clock Rate =', fpga.estimate_fpga_clock()
fpga.get_system_information()
results = {}
for qdr in fpga.qdrs:
print qdr
mqdr = myQdr.from_qdr(qdr)
results[qdr.name] = mqdr.qdr_cal2(fail_hard=bFailHard,
verbosity=calVerbosity)
print 'qdr cal results:', results
for qdrName in ['qdr0', 'qdr1']:
if not results[qdr.name]:
print 'Calibration Failed'
break
time.sleep(1)
return
fpga = casperfpga.katcp_fpga.KatcpFpga(ip,timeout=50.)
if not fpga.is_running():
fpgPath = os.environ['FPG_PATH']
print 'Programming board with fpg:',fpgPath
fpga.upload_to_ram_and_program(fpgPath)
print 'Fpga Clock Rate:',fpga.estimate_fpga_clock()
bQdrCal = True
if bQdrCal:
bFailHard = False
fpga.get_system_information()
results = {}
for iQdr,qdr in enumerate(fpga.qdrs):
mqdr = myQdr.from_qdr(qdr)
print qdr.name
results[qdr.name] = mqdr.qdr_cal2(fail_hard=bFailHard,verbosity=calVerbosity)
print 'Qdr cal results:',results
for qdrName in results.keys():
if not results[qdrName]:
exit(1)
time.sleep(1)
print 'done!'
roachController.fpga.write_int('adc_in_i_scale',
2**7) # set relative IQ scaling to 1
roachController.fpga.write_int('run', 1)
busDelays = [14, 18, 14, 13]
busStarts = [0, 14, 28, 42]
busBitLength = 12
for iBus in xrange(len(busDelays)):
print "iBus =", iBus
delayLut = zip(np.arange(busStarts[iBus], busStarts[iBus] + busBitLength),
busDelays[iBus] * np.ones(busBitLength))
print "delayLut =", delayLut
loadDelayCal(roachController.fpga, delayLut)
print "done with iBus =", iBus
calDict = findCal(roachController.fpga)
print "calDict=", calDict
roachController.sendUARTCommand(0x5)
print 'switched off ADC ZDOK Cal ramp'
# Calibrate QDR
print "===>Calibrate QDR"
calVerbosity = 0
bFailHard = False
results = {}
for iQdr, qdr in enumerate(roachController.fpga.qdrs):
mqdr = myQdr.from_qdr(qdr)
results[qdr.name] = mqdr.qdr_cal2(fail_hard=bFailHard,
verbosity=calVerbosity)
print 'Qdr cal results:', results
def init(roachNumber, configFile):
"""
Initialize the Roach board after powering up:
Upload the program from the config parameter 'fpgPath'
Call Roach2Controls.loadBoardNum and loadCurTimestamp
Call Roach2Controls.initializeV7UART
Call Roach2Controls.initializeV7MB
Call Roach2Controls.setLOFreq() then .loadLOFreq
Call Roach2Controls.changeAtten for DAC atten 1&2, ADC atten 1&2 (all to 31.75)
Call Roach2Controls.sendUARTCommand(0x4) to switch on ADC ZDOK Cal Ramp
set relative IQ scaling to 1
Call Roach2Controls.fpga.write_int('run',1)
do delays and calibrations
Call Roach2Controls.sendUARTCommand(0x5) to switch off ADC ZDOK Cal Ramp
run QDR calibrations
call clTools.connect() to define rchc
rchc.defineRoachLUTs
rchc.loadFIRs
Return -- the resulting rchc
"""
config = ConfigParser.ConfigParser()
config.read(configFile)
# Mimic what is done in InitStateMachine programV6
roachString = 'Roach ' + "%d" % roachNumber
FPGAParamFile = config.get(roachString, 'FPGAParamFile')
ipaddress = config.get(roachString, 'ipaddress')
roachController = Roach2Controls.Roach2Controls(ipaddress, FPGAParamFile,
False, False)
roachController.connect()
fpgPath = config.get('Roach ' + str(roachNumber), 'fpgPath')
print "set casperfpga.utils logger to INFO"
casperfpga.utils.LOGGER.setLevel(logging.INFO)
print "loading firmware", fpgPath
roachController.fpga.upload_to_ram_and_program(fpgPath)
print 'Fpga Clock Rate:', roachController.fpga.estimate_fpga_clock()
roachController.loadBoardNum(roachNumber)
roachController.loadCurTimestamp()
# Mimic what is done in InitStateMachine initV7
waitForV7Ready = config.getboolean('Roach ' + str(roachNumber),
'waitForV7Ready')
roachController.initializeV7UART(waitForV7Ready=waitForV7Ready)
print 'initialized uart'
roachController.initV7MB()
print 'initialized mb'
#self.config.set('Roach '+str(roachNumber),'waitForV7Ready',False)
roachController.setLOFreq(2.e9)
roachController.loadLOFreq()
print 'Set LO to 2 GHz'
roachController.changeAtten(1, 31.75) #DAC atten 1
roachController.changeAtten(2, 31.75) #DAC atten 2
roachController.changeAtten(3, 31.75) #ADC atten 1
roachController.changeAtten(4, 31.75) #ADC atten 2
print 'Set RF board attenuators to maximum'
# Mimic what is done in InitStateMachine calZdok
roachController.sendUARTCommand(0x4)
print 'switched on ADC ZDOK Cal ramp'
time.sleep(.1)
nBitsRemovedInFFT = config.getint('Roach ' + str(roachNumber),
'nBitsRemovedInFFT')
roachController.fpga.write_int('adc_in_i_scale',
2**7) #set relative IQ scaling to 1
# if(nBitsRemovedInFFT == 0):
# rchc.setAdcScale(0.9375) #Max ADC scale value
# else:
# rchc.setAdcScale(1./(2**nBitsRemovedInFFT))
roachController.fpga.write_int('run', 1)
busDelays = [14, 18, 14, 13]
busStarts = [0, 14, 28, 42]
busBitLength = 12
for iBus in xrange(len(busDelays)):
delayLut = zip(
np.arange(busStarts[iBus], busStarts[iBus] + busBitLength),
busDelays[iBus] * np.ones(busBitLength))
loadDelayCal(roachController.fpga, delayLut)
# calDict = findCal(roachController.fpga,nBitsRemovedInFFT)
calDict = findCal(roachController.fpga)
print calDict
roachController.sendUARTCommand(0x5)
print 'switched off ADC ZDOK Cal ramp'
if not calDict['solutionFound']:
raise ValueError
# Mimic what is done in InitStateMachine calQDR
bQdrFlip = True
calVerbosity = 0
bFailHard = False
#roachController.fpga.get_system_information()
results = {}
for iQdr, qdr in enumerate(roachController.fpga.qdrs):
mqdr = myQdr.from_qdr(qdr)
print qdr.name
results[qdr.name] = mqdr.qdr_cal2(fail_hard=bFailHard,
verbosity=calVerbosity)
print 'Qdr cal results:', results
for qdrName in results.keys():
if not results[qdrName]:
raise ValueError
rchc = connect(roachNumber, configFile)
rchc.loadFIRs()
return rchc