def __call__(self, func, *args, **kwargs):
global _converting
if _converting:
return func(*args, **kwargs) # skip
else:
# clean start
sys.setprofile(None)
from myhdl import _traceSignals
if _traceSignals._tracing:
raise ToVerilogError("Cannot use toVerilog while tracing signals")
if not callable(func):
raise ToVerilogError(_error.FirstArgType, "got %s" % type(func))
_converting = 1
if self.name is None:
name = func.func_name
else:
name = str(self.name)
try:
h = _HierExtr(name, func, *args, **kwargs)
finally:
_converting = 0
vpath = name + ".v"
vfile = open(vpath, 'w')
### initialize properly ###
_genUniqueSuffix.reset()
arglist = _flatten(h.top)
# print h.top
_checkArgs(arglist)
genlist = _analyzeGens(arglist, h.absnames)
siglist, memlist = _analyzeSigs(h.hierarchy)
_annotateTypes(genlist)
top_inst = h.hierarchy[0]
intf = _analyzeTopFunc(top_inst, func, *args, **kwargs)
doc = _makeDoc(inspect.getdoc(func))
self._convert_filter(h, intf, siglist, memlist, genlist)
_writeFileHeader(vfile, vpath, self.timescale)
_writeModuleHeader(vfile, intf, doc)
_writeSigDecls(vfile, intf, siglist, memlist)
_convertGens(genlist, vfile)
_writeModuleFooter(vfile)
vfile.close()
# don't write testbench if module has no ports
if len(intf.argnames) > 0 and not toVerilog.no_testbench:
tbpath = "tb_" + vpath
tbfile = open(tbpath, 'w')
_writeTestBench(tbfile, intf)
tbfile.close()
### clean-up properly ###
self._cleanup(siglist)
return h.top
def _inferInterface(self):
from myhdl.conversion._analyze import _analyzeTopFunc
intf = _analyzeTopFunc(self.func, *self.args, **self.kwargs)
self.argnames = intf.argnames
self.argdict = intf.argdict
def _inferInterface(self):
from myhdl.conversion._analyze import _analyzeTopFunc
intf = _analyzeTopFunc(self.func, *self.args, **self.kwargs)
self.argnames = intf.argnames
self.argdict = intf.argdict
def __call__(self, func, *args, **kwargs):
global _converting
if _converting:
return func(*args, **kwargs) # skip
else:
# clean start
sys.setprofile(None)
from myhdl import _traceSignals
if _traceSignals._tracing:
raise ToVerilogError("Cannot use toVerilog while tracing signals")
if not callable(func):
raise ToVerilogError(_error.FirstArgType, "got %s" % type(func))
_converting = 1
if self.name is None:
name = func.__name__
else:
name = str(self.name)
try:
h = _HierExtr(name, func, *args, **kwargs)
finally:
_converting = 0
if self.directory is None:
directory = ''
else:
directory = self.directory
vfilename = name + ".v"
vpath = os.path.join(directory, vfilename)
vfile = open(vpath, 'w')
### initialize properly ###
_genUniqueSuffix.reset()
arglist = _flatten(h.top)
# print h.top
_checkArgs(arglist)
genlist = _analyzeGens(arglist, h.absnames)
siglist, memlist = _analyzeSigs(h.hierarchy)
_annotateTypes(genlist)
top_inst = h.hierarchy[0]
intf = _analyzeTopFunc(top_inst, func, *args, **kwargs)
intf.name = name
doc = _makeDoc(inspect.getdoc(func))
self._convert_filter(h, intf, siglist, memlist, genlist)
_writeFileHeader(vfile, vpath, self.timescale)
_writeModuleHeader(vfile, intf, doc)
_writeSigDecls(vfile, intf, siglist, memlist)
_convertGens(genlist, vfile)
_writeModuleFooter(vfile)
vfile.close()
# don't write testbench if module has no ports
if len(intf.argnames) > 0 and not toVerilog.no_testbench:
tbpath = os.path.join(directory, "tb_" + vfilename)
tbfile = open(tbpath, 'w')
_writeTestBench(tbfile, intf, self.trace)
tbfile.close()
# build portmap for cosimulation
portmap = {}
for n, s in intf.argdict.items():
if hasattr(s, 'driver'): portmap[n] = s.driver()
else: portmap[n] = s
self.portmap = portmap
### clean-up properly ###
self._cleanup(siglist)
return h.top
def __call__(self, func, *args, **kwargs):
global _converting
if _converting:
return func(*args, **kwargs) # skip
else:
# clean start
sys.setprofile(None)
from myhdl import _traceSignals
if _traceSignals._tracing:
raise ToVerilogError("Cannot use toVerilog while tracing signals")
if not callable(func):
raise ToVerilogError(_error.FirstArgType, "got %s" % type(func))
_converting = 1
if self.name is None:
name = func.func_name
else:
name = str(self.name)
try:
h = _HierExtr(name, func, *args, **kwargs)
finally:
_converting = 0
vpath = name + ".v"
vfile = open(vpath, 'w')
### initialize properly ###
_genUniqueSuffix.reset()
siglist, memlist = _analyzeSigs(h.hierarchy)
arglist = _flatten(h.top)
# print h.top
_checkArgs(arglist)
genlist = _analyzeGens(arglist, h.absnames)
intf = _analyzeTopFunc(func, *args, **kwargs)
intf.name = name
_writeFileHeader(vfile, vpath, self.timescale)
_writeModuleHeader(vfile, intf)
_writeSigDecls(vfile, intf, siglist, memlist)
_convertGens(genlist, vfile)
_writeModuleFooter(vfile)
vfile.close()
# don't write testbench if module has no ports
if len(intf.argnames) > 0:
tbpath = "tb_" + vpath
tbfile = open(tbpath, 'w')
_writeTestBench(tbfile, intf)
tbfile.close()
# clean up signal names
for sig in siglist:
sig._name = None
sig._driven = False
sig._read = False
# clean up attributes
self.name = None
return h.top
def __call__(self, func, *args, **kwargs):
global _converting
if _converting:
return func(*args, **kwargs) # skip
else:
# clean start
sys.setprofile(None)
from myhdl import _traceSignals
if _traceSignals._tracing:
raise ToVerilogError("Cannot use toVerilog while tracing signals")
if not callable(func):
raise ToVerilogError(_error.FirstArgType, "got %s" % type(func))
_converting = 1
if self.name is None:
name = func.__name__
else:
name = str(self.name)
try:
h = _HierExtr(name, func, *args, **kwargs)
finally:
_converting = 0
if self.directory is None:
directory = ''
else:
directory = self.directory
vfilename = name + ".v"
vpath = os.path.join(directory, vfilename)
vfile = open(vpath, 'w')
### initialize properly ###
_genUniqueSuffix.reset()
arglist = _flatten(h.top)
# print h.top
_checkArgs(arglist)
genlist = _analyzeGens(arglist, h.absnames)
siglist, memlist = _analyzeSigs(h.hierarchy)
_annotateTypes(genlist)
intf = _analyzeTopFunc(func, *args, **kwargs)
intf.name = name
doc = _makeDoc(inspect.getdoc(func))
self._convert_filter(h, intf, siglist, memlist, genlist)
_writeFileHeader(vfile, vpath, self.timescale)
_writeModuleHeader(vfile, intf, doc)
_writeSigDecls(vfile, intf, siglist, memlist)
_convertGens(genlist, vfile)
_writeModuleFooter(vfile)
vfile.close()
# don't write testbench if module has no ports
if len(intf.argnames) > 0 and not toVerilog.no_testbench:
tbpath = os.path.join(directory, "tb_" + vfilename)
tbfile = open(tbpath, 'w')
_writeTestBench(tbfile, intf, self.trace)
tbfile.close()
# build portmap for cosimulation
portmap = {}
for n, s in intf.argdict.items():
if hasattr(s, 'driver'): portmap[n] = s.driver()
else: portmap[n] = s
self.portmap = portmap
### clean-up properly ###
self._cleanup(siglist)
return h.top