Exemplo n.º 1
0
def prep_cosim(clock, reset, datai, datao, args=None):
    spth = './reference_designs/jpegenc_v1/verilog'
    filelist = [
        'DCT1D.v', 'DCT2D.v', 'DBUFCTL.v', 'RAM.v', 'ROME.v', 'ROMO.v',
        'MDCT.v'
    ]

    filelist = [os.path.join(spth, ff) for ff in filelist]
    filelist += ['tb_mdct.v']

    for ff in filelist:
        assert os.path.isfile(ff), "%s" % (ff, )

    cmd = "iverilog -g2001 -o mdct %s" % (" ".join(filelist))
    os.system(cmd)

    cmd = "vvp -m ./myhdl.vpi -lxt2 mdct"
    gcosim = myhdl.Cosimulation(cmd,
                                clock=clock,
                                reset=reset,
                                dcti=datai.data,
                                idv=datai.dv,
                                dcto=datao.data,
                                odv=datao.dv)

    return gcosim
Exemplo n.º 2
0
 def banner_compilation():
     os.system(cmd1)
     return hdl.Cosimulation(cmd2,
                             clk=clk,
                             rst=rst,
                             anodos=anodos,
                             segmentos=segmentos,
                             shift=shift)
Exemplo n.º 3
0
 def compilation():
     os.system(cmd1)
     return hdl.Cosimulation(cmd2,
                             clk_i=clk,
                             rst_i=rst,
                             rx_i=rx,
                             tx_o=tx,
                             anodos_o=anodos,
                             segmentos_o=segmentos)
 def alu_compilation(A, B, OP, result, invalid):
     """
     Función 'local' auxiliar.
     """
     os.system(cmd1)
     return hdl.Cosimulation(cmd2,
                             A=A,
                             B=B,
                             OP=OP,
                             result=result,
                             invalid=invalid)
Exemplo n.º 5
0
 def dutgen(self, test):
     """Cosimulation of actual Verilog code"""
     # This is because icarus does not allow changing the dumpfile in
     # a nice way
     oldpath = os.getcwd()
     newpath = os.path.join(oldpath, test.__name__)
     os.makedirs(newpath, exist_ok=True)
     os.chdir(newpath)
     ret = myhdl.Cosimulation(
         "vvp -m myhdl ../test.vvp -fst",
         clk=self.clk,
         reset=self.rst,
         rx_st_data=self.ep.rx_st_data,
         rx_st_empty=self.ep.rx_st_empty,
         rx_st_error=self.ep.rx_st_error,
         rx_st_startofpacket=self.ep.rx_st_startofpacket,
         rx_st_endofpacket=self.ep.rx_st_endofpacket,
         rx_st_ready=self.ep.rx_st_ready,
         rx_st_valid=self.ep.rx_st_valid,
         rx_st_bar=self.ep.rx_st_bar,
         rx_st_mask=self.ep.rx_st_mask,
         tx_st_data=self.ep.tx_st_data,
         tx_st_startofpacket=self.ep.tx_st_startofpacket,
         tx_st_endofpacket=self.ep.tx_st_endofpacket,
         tx_st_error=self.ep.tx_st_error,
         tx_st_empty=self.ep.tx_st_empty,
         tx_st_ready=self.ep.tx_st_ready,
         tx_st_valid=self.ep.tx_st_valid,
         data_tx_data=self.data_tx_data,
         data_tx_valid=self.data_tx_valid,
         data_tx_ready=self.data_tx_ready,
         data_tx_channel=self.data_tx_channel,
         data_tx_endofpacket=self.data_tx_endofpacket,
         data_tx_startofpacket=self.data_tx_startofpacket,
         data_tx_empty=self.data_tx_empty,
         tl_cfg_add=self.ep.tl_cfg_add,
         tl_cfg_ctl=self.ep.tl_cfg_ctl,
         tl_cfg_sts=self.ep.tl_cfg_sts)
     os.chdir(oldpath)
     return ret