def TestBench(MCP3008Tester):
ch1 = Signal(intbv(0)[10:])
ch2 = Signal(intbv(0)[10:])
ch3 = Signal(intbv(0)[10:])
ch4 = Signal(intbv(0)[10:])
ch5 = Signal(intbv(0)[10:])
ch6 = Signal(intbv(0)[10:])
ch7 = Signal(intbv(0)[10:])
ch8 = Signal(intbv(0)[10:])
spi_clk = Signal(LOW)
spi_ss_n = Signal(HIGH)
spi_miso = Signal(LOW)
spi_mosi = Signal(LOW)
clk = Signal(LOW)
rst_n = Signal(HIGH)
MCP3008Driver_inst = traceSignals(MCP3008Driver,
ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8,
spi_clk, spi_ss_n, spi_miso, spi_mosi, clk, rst_n)
MCP3008Tester_inst = MCP3008Tester(
ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8,
spi_clk, spi_ss_n, spi_miso, spi_mosi, clk, rst_n)
ClkGen_inst = ClkGen(clk)
return MCP3008Driver_inst, MCP3008Tester_inst, ClkGen_inst
def TestBench(MCP3008Tester):
ch1 = Signal(intbv(0)[10:])
ch2 = Signal(intbv(0)[10:])
ch3 = Signal(intbv(0)[10:])
ch4 = Signal(intbv(0)[10:])
ch5 = Signal(intbv(0)[10:])
ch6 = Signal(intbv(0)[10:])
ch7 = Signal(intbv(0)[10:])
ch8 = Signal(intbv(0)[10:])
spi_clk = Signal(LOW)
spi_ss_n = Signal(HIGH)
spi_miso = Signal(LOW)
spi_mosi = Signal(LOW)
clk = Signal(LOW)
rst_n = Signal(HIGH)
MCP3008Driver_inst = traceSignals(MCP3008Driver, ch1, ch2, ch3, ch4, ch5,
ch6, ch7, ch8, spi_clk, spi_ss_n,
spi_miso, spi_mosi, clk, rst_n)
MCP3008Tester_inst = MCP3008Tester(ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8,
spi_clk, spi_ss_n, spi_miso, spi_mosi,
clk, rst_n)
ClkGen_inst = ClkGen(clk)
return MCP3008Driver_inst, MCP3008Tester_inst, ClkGen_inst
def run_testbench(tbfunc, mexname='', dutmod=None, portmap=None):
"""
Arguments:
tbfunc: testbench function
dutmod: design under test module (function)
mexname: name of the exercise (name of the VCD file)
portmap: dictionary with the top-level port map for conversion
"""
if not os.path.isdir('vcd'):
os.makedirs('vcd')
traceSignals.name = 'vcd/{}'.format(mexname)
if os.path.isfile(traceSignals.name + '.vcd'):
os.remove(traceSignals.name + '.vcd')
Simulation(traceSignals(tbfunc)).run()
noerror = hasattr(tbfunc, 'error') and not tbfunc.error
if dutmod is not None and portmap is not None and noerror:
if not os.path.isdir('output'):
os.makedirs('output')
myhdl.toVHDL.directory = 'output'
myhdl.toVerilog.directory = 'output'
myhdl.toVerilog.no_testbench = True
myhdl.toVHDL(dutmod, **portmap)
myhdl.toVerilog(dutmod, **portmap)
def run_IM_cosim():
# Initiate signals
MAX_TIME = 1000000
clock = Signal(0)
MR = Signal(0, delay=10)
MW = Signal(0, delay=10)
address = Signal(intbv(0, 0, 2**32), delay=10)
WD = Signal(intbv(0, 0, 2**32), delay=10)
pyData = Signal(intbv(0, 0, 2**32))
vData = Signal(intbv(0, 0, 2**32))
# Build driver instances
clock_driver = clock_generator(clock, period=20)
addr_driver = random_signal(clock, address, seed=1)
WD_driver = random_signal(clock, WD, seed=2)
MR_driver = pulse_generator(clock, MR, delay=2)
MW_driver = pulse_generator(clock, MW, delay=3)
py_cosim = traceSignals(py_dm(clock, address, MW, MR, pyData, WD))
v_cosim = v_dm(clock, MR, MW, address, WD, vData)
read_test = match_test_report(clock,
vData,
pyData,
a_name="v:",
b_name="py:")
sim = Simulation(instances())
sim.run(MAX_TIME)
def run_sim(self, duration=None, quiet=0):
if self.sim is None:
sim = self
if self._config_sim['trace']:
sim = myhdl.traceSignals(self)
self.sim = myhdl._Simulation.Simulation(sim)
self.sim.run(duration, quiet)
def test_simulate(self):
import myhdl
duration=1
def _sim():
pix = Add_shift_top(duration=duration)
pix_presetn = pix.presetn
pix_pclk = pix.pclk
pix_paddr = pix.paddr
pix_psel = pix.psel
pix_penable = pix.penable
pix_pwrite = pix.pwrite
pix_pwdata = pix.pwdata
pix_pready = pix.pready
pix_prdata = pix.prdata
pix_pslverr = pix.pslverr
@myhdl.instance
def __sim():
yield pix.reset()
yield pix.transmit(0x4000, 0x0110)
return __sim
s = myhdl.Simulation(myhdl.traceSignals(_sim))
s.run(10000)
def main_simulate():
resetn = Signal(bool(1))
system_clock = Signal(bool(0))
paddr = Signal(intbv(0, 0, 2**32))
psel = Signal(bool(0))
penable = Signal(bool(0))
pwrite = Signal(bool(1))
pwdata = Signal(intbv(0, 0, 2**32))
pready = Signal(bool(0))
prdata = Signal(intbv(0, 0, 2**32))
pslverr = Signal(bool(0))
apb3_bus_signals = [system_clock, resetn, paddr, psel, penable, pwrite,
pwdata, pready, prdata, pslverr]
SYSTEM_CLOCK_FREQ = 10e6
SYSTEM_CLOCK_PERIOD_IN_NS = int(1.0 / SYSTEM_CLOCK_FREQ * 1e9)
def testbench():
clock = drive_system_clock(system_clock, SYSTEM_CLOCK_PERIOD_IN_NS)
reset = drive_reset(resetn)
master = apb3_master_mock([(0x40050400, 0xffffffff),
(0x40050400, 0xffff7fff)],
*apb3_bus_signals)
slave = fluidsp_controller(*(apb3_bus_signals))
return clock, reset, slave, master
traced_testbench = traceSignals(testbench)
sim = Simulation(traced_testbench)
sim.run(SYSTEM_CLOCK_PERIOD_IN_NS * 100)
def run_sim(self, duration=None, quiet=0):
if self.sim is None:
sim = self
if self._config_sim['trace']:
sim = myhdl.traceSignals(self)
self.sim = myhdl._Simulation.Simulation(sim)
self.sim.run(duration, quiet)
def test_simulate(self):
import myhdl
duration=1
def _sim():
bus = Apb3Bus(duration=duration)
bus_presetn = bus.presetn
bus_pclk = bus.pclk
bus_paddr = bus.paddr
bus_psel = bus.psel
bus_penable = bus.penable
bus_pwrite = bus.pwrite
bus_pwdata = bus.pwdata
bus_pready = bus.pready
bus_prdata = bus.prdata
bus_pslverr = bus.pslverr
@myhdl.instance
def __sim():
yield bus.reset()
yield bus.transmit(0x4000, 0x0110)
return __sim
s = myhdl.Simulation(myhdl.traceSignals(_sim))
s.run(10000)
def run_ALU_cosim():
# Initiate signals
MAX_TIME = 1000000
clock = Signal(0)
reset = Signal(0)
inA = Signal(intbv(0, 0, 2**32), delay=10)
inB = Signal(intbv(0, 0, 2**32), delay=10)
ALU_control = Signal(intbv(0, 0, 2**3), delay=10)
pyData = Signal(intbv(0, 0, 2**32))
pyZero = Signal(intbv(0, 0, 2**32))
vData = Signal(intbv(0, 0, 2**32))
vZero = Signal(intbv(0, 0, 2**32))
# Build driver instances
clock_driver = clock_generator(clock, period=20)
control_driver = random_signal(clock, ALU_control, seed=1)
A_rand = random_signal(clock, inA, seed=2)
B_rand = random_signal(clock, inB, seed=3)
reset_driver = pulse_generator(clock, reset)
py_cosim = traceSignals(
py_alu(clock, reset, inA, inB, ALU_control, pyData, pyZero))
v_cosim = v_alu(clock, reset, ALU_control, inA, inB, vData, vZero)
read_test = match_test_report(clock, (vData, vZero), (pyData, pyZero),
a_name="v:",
b_name="py:")
sim = Simulation(instances())
sim.run(MAX_TIME)
def sim():
insts = []
insts.append(traceSignals(gen, *args))
insts.append(stimuli())
sim = Simulation(insts)
sim.run(duration)
print
sys.stdout.flush()
def testBench():
if not DEBUG:
datapath_i = traceSignals(pipeline) # () #toVHDL(datapath)
else:
datapath_i = pipeline()
return instances()
def testBench():
if not DEBUG:
datapath_i = traceSignals(dlx) #() #toVHDL(datapath)
else:
datapath_i = dlx()
return instances()
def testBench():
if not DEBUG:
datapath_i = traceSignals(pipeline) # () #toVHDL(datapath)
else:
datapath_i = pipeline()
return instances()
def sim():
insts = []
insts.append(traceSignals(gen, *args))
insts.append(stimuli())
sim = Simulation(insts)
sim.run(duration)
print
sys.stdout.flush()
def __call__(self):
if self.trace:
#traceSignals.timescale = toMyHDL.timescale
traceSignals.name = self.name
gen = traceSignals(self.top, *self.args, **self.kwargs)
else:
gen = self.top(*self.args, **self.kwargs)
return gen
def __call__(self):
if self.trace:
#traceSignals.timescale = toMyHDL.timescale
traceSignals.name = self.name
gen = traceSignals(self.top, *self.args, **self.kwargs)
else:
gen = self.top(*self.args, **self.kwargs)
return gen
def sim():
from myhdl import Simulation, traceSignals
import sys
test_inst = traceSignals(create_test)
sim = Simulation(test_inst)
sim.run(20000)
print
sys.stdout.flush()
def sim(self):
insts = []
insts.append(traceSignals(self.gen, *self.args))
insts += self.stimuli
sim = Simulation(insts)
sim.run(self.duration)
print
sys.stdout.flush()
def sim(self):
insts = []
insts.append(traceSignals(self.gen, *self.args))
insts += self.stimuli
sim = Simulation(insts)
sim.run(self.duration)
print
sys.stdout.flush()
def sim():
from myhdl import Simulation, traceSignals
import sys
test_inst = traceSignals(create_test)
sim = Simulation(test_inst)
sim.run(20000)
print
sys.stdout.flush()
def simulate_quadrature(self, in_i, in_q, dspflow, **kwargs):
"""Actually run the simulation, with separate i and q inputs.
:param in_i: The input i sequence.
:param in_q: The input q sequence.
:param dspflow: The MyHDL module representing the dsp flow.
:param interp: How many samples to zero-stuff.
:returns: The valid i and q sequences as a tuple.
"""
interp = kwargs.get('interp', 1)
loader = kwargs.get('loader', None)
@instance
def stimulus():
self.t = 0
if loader:
yield loader()
self.clearn.next = self.clearn.active
yield self.delay(1)
self.clearn.next = not self.clearn.active
while self.t < len(in_i):
yield self.produce(self.input.myhdl(in_i[self.t]),
self.input.myhdl(in_q[self.t]), interp)
self.t = self.t + 1
self.input.valid.next = False
yield self.delay(1)
while self.output.valid:
self.consume()
yield self.delay(1)
raise StopSimulation
# Show the input
#f_chain_in = figure_discrete_quadrature("chain in", 223, f, self.input, in_n, in_i, in_q)
traced = traceSignals(dspflow)
recordings = [
s.record(self.clearn, self.clock) for s in self.recording
]
s = Simulation(stimulus, recordings, traced)
s.run()
final_i, final_q = (np.array(self.results_i,
dtype=self.output.numpy_dtype()),
np.array(self.results_q,
dtype=self.output.numpy_dtype()))
assert len(final_i) == len(final_q)
final_n = np.arange(final_i.shape[0])
#f_chain_out = figure_discrete_quadrature("chain out", 224, f, self.output, final_n, final_i, final_q)
return final_i, final_q
def test_memory():
"""
Memory: Test load and R/W operations.
"""
gen_test_file()
trace = False
if trace:
sim = Simulation(traceSignals(_testbench))
else:
sim = Simulation(_testbench())
sim.run()
def test_core(hex_file, vcd):
"""
Core: Behavioral test for the RISCV core.
"""
if vcd:
vcd = traceSignals(core_testbench, hex_file,)
sim = Simulation(vcd)
else:
sim = Simulation(core_testbench(hex_file))
sim.run()
def sim(visu = False):
try:
os.remove('_bench.vcd')
except Exception as e:
pass # just ignore, the file is probably not here.
fsm = traceSignals(testbench())
sim = Simulation(fsm)
sim.run()
if visu:
call(['gtkwave', '_bench.vcd'])
def sim(visu=False):
try:
os.remove('_bench.vcd')
except Exception as e:
pass # just ignore, the file is probably not here.
fsm = traceSignals(testbench())
sim = Simulation(fsm)
sim.run()
if visu:
call(['gtkwave', '_bench.vcd'])
def testBench():
if not DEBUG:
datapath_i = traceSignals(dlx) #() #toVHDL(datapath)
else:
datapath_i = dlx()
return instances()
def test_memory():
"""
Memory: Test load and R/W operations.
"""
gen_test_file()
trace = False
if trace:
sim = Simulation(traceSignals(_testbench))
else:
sim = Simulation(_testbench())
sim.run()
def test_cache():
"""
Cache: Test loading from memory
"""
gen_test_file()
trace = False
if trace:
sim = Simulation(traceSignals(_testbench))
else:
sim = Simulation(_testbench())
sim.run()
def main():
args = cliparse()
if args.trace:
mosi, miso, sck, ss = Signals(bool(0), 4)
led = Signal(bool(0))
clock=Clock(0, frequency=50e6)
tb_fsm = traceSignals(tb,led, clock, mosi, miso, sck, ss, reset=None)
sim = Simulation(tb_fsm)
sim.run()
if args.build:
build(args)
def test_cache():
"""
Cache: Test loading from memory
"""
gen_test_file()
trace = False
if trace:
sim = Simulation(traceSignals(_testbench))
else:
sim = Simulation(_testbench())
sim.run()
def simulate(self, stimulus, whitebox, **kwargs):
"""Acturally run the cosimulation with iverilog.
:param stimulus: A callable that returns the cosim object.
:param whitebox: A whitebox peripheral object.
:param record_tx: Record the passed in number of valid samples.
:param auto_stop: Raise ``StopSimulation`` when the correct number of samples have been recorded.
:param sample_rate: Samples per second.
"""
record_tx = kwargs.get('record_tx', None)
auto_stop = kwargs.get('auto_stop', False)
self.sample_rate = kwargs.get('sample_rate', 10e6)
DAC2X_DURATION = int(1e9 / (self.sample_rate * 2))
DAC_DURATION = int(1e9 / self.sample_rate)
@instance
def dac2x_clock():
while True:
self.dac2x_clock.next = not self.dac2x_clock
yield delay(DAC2X_DURATION // 2)
@instance
def dac_clock():
yield delay(DAC2X_DURATION // 4)
while True:
self.dac_clock.next = not self.dac_clock
yield delay(DAC_DURATION // 2)
@always(self.dac_clock.posedge,
self.dac_clock.negedge,
self.bus.presetn.negedge)
def tx_recorder():
if not self.bus.presetn:
self.tx_q = []
self.tx_i = []
self.tx_n = []
elif len(self.tx_i) == len(self.tx_q) and len(self.tx_i) == record_tx:
if auto_stop:
raise StopSimulation
elif self.dac_en:
if self.dac_clock:
self.tx_q.append(int(self.dac_data[:]))
self.tx_n.append(now())
else:
self.tx_i.append(int(self.dac_data[:]))
traced = traceSignals(whitebox)
ss = [dac_clock, dac2x_clock, stimulus, traced]
if 'record_tx' in kwargs:
ss.append(tx_recorder)
s = Simulation(ss)
s.run()
def simulate(self, stimulus, whitebox, **kwargs):
"""Acturally run the cosimulation with iverilog.
:param stimulus: A callable that returns the cosim object.
:param whitebox: A whitebox peripheral object.
:param record_tx: Record the passed in number of valid samples.
:param auto_stop: Raise ``StopSimulation`` when the correct number of samples have been recorded.
:param sample_rate: Samples per second.
"""
record_tx = kwargs.get('record_tx', None)
auto_stop = kwargs.get('auto_stop', False)
self.sample_rate = kwargs.get('sample_rate', 10e6)
DAC2X_DURATION = int(1e9 / (self.sample_rate * 2))
DAC_DURATION = int(1e9 / self.sample_rate)
@instance
def dac2x_clock():
while True:
self.dac2x_clock.next = not self.dac2x_clock
yield delay(DAC2X_DURATION // 2)
@instance
def dac_clock():
yield delay(DAC2X_DURATION // 4)
while True:
self.dac_clock.next = not self.dac_clock
yield delay(DAC_DURATION // 2)
@always(self.dac_clock.posedge, self.dac_clock.negedge,
self.bus.presetn.negedge)
def tx_recorder():
if not self.bus.presetn:
self.tx_q = []
self.tx_i = []
self.tx_n = []
elif len(self.tx_i) == len(self.tx_q) and len(
self.tx_i) == record_tx:
if auto_stop:
raise StopSimulation
elif self.dac_en:
if self.dac_clock:
self.tx_q.append(int(self.dac_data[:]))
self.tx_n.append(now())
else:
self.tx_i.append(int(self.dac_data[:]))
traced = traceSignals(whitebox)
ss = [dac_clock, dac2x_clock, stimulus, traced]
if 'record_tx' in kwargs:
ss.append(tx_recorder)
s = Simulation(ss)
s.run()
def simulate_quadrature(self, in_i, in_q, dspflow, **kwargs):
"""Actually run the simulation, with separate i and q inputs.
:param in_i: The input i sequence.
:param in_q: The input q sequence.
:param dspflow: The MyHDL module representing the dsp flow.
:param interp: How many samples to zero-stuff.
:returns: The valid i and q sequences as a tuple.
"""
interp = kwargs.get('interp', 1)
loader = kwargs.get('loader', None)
@instance
def stimulus():
self.t = 0
if loader:
yield loader()
self.clearn.next = self.clearn.active
yield self.delay(1)
self.clearn.next = not self.clearn.active
while self.t < len(in_i):
yield self.produce(self.input.myhdl(in_i[self.t]),
self.input.myhdl(in_q[self.t]), interp)
self.t = self.t + 1
self.input.valid.next = False
yield self.delay(1)
while self.output.valid:
self.consume()
yield self.delay(1)
raise StopSimulation
# Show the input
#f_chain_in = figure_discrete_quadrature("chain in", 223, f, self.input, in_n, in_i, in_q)
traced = traceSignals(dspflow)
recordings = [s.record(self.clearn, self.clock) for s in self.recording]
s = Simulation(stimulus, recordings, traced)
s.run()
final_i, final_q = (np.array(self.results_i, dtype=self.output.numpy_dtype()),
np.array(self.results_q, dtype=self.output.numpy_dtype()))
assert len(final_i) == len(final_q)
final_n = np.arange(final_i.shape[0])
#f_chain_out = figure_discrete_quadrature("chain out", 224, f, self.output, final_n, final_i, final_q)
return final_i, final_q
def test_core(hex_file, vcd):
"""
Core: Behavioral test for the RISCV core.
"""
if vcd:
vcd = traceSignals(
core_testbench,
hex_file,
)
sim = Simulation(vcd)
else:
sim = Simulation(core_testbench(hex_file))
sim.run()
def sim():
from myhdl import Simulation, traceSignals
insts, test_gen, test_args = setup()
test_inst = traceSignals(test_gen, *test_args)
insts.append(test_inst)
if 1:
reader_inst = reader(test_args[0], test_args[1], 64, 123 * nsec)
insts.append(reader_inst)
sim = Simulation(*insts)
sim.run(5 * usec)
def testBench(width):
B = Signal(intbv(0))
G = Signal(intbv(0))
dut = traceSignals(bin2gray, B, G, width)
@instance
def stimulus():
for i in range(2**width):
B.next = intbv(i)
yield delay(10)
print "B: " + bin(B, width) + "| G: " + bin(G, width)
return dut, stimulus
def test_core(hex_file, vcd):
"""
Core: Behavioral test for the RISCV core.
"""
if vcd:
vcd = traceSignals(core_testbench, hex_file,)
sim = Simulation(vcd)
else:
sim = Simulation(core_testbench(hex_file))
sim.run()
# Local Variables:
# flycheck-flake8-maximum-line-length: 120
# flycheck-flake8rc: ".flake8rc"
# End:
def simulate(sim_temp_dir, sim_pattern_dir, valid_pattern, ready_pattern, nb_frames,sim_time=None):
print("Start Myhdl Simulation....................................")
cwd=os.getcwd()
os.chdir(sim_temp_dir)
inst.sim_defaults(sim_temp_dir)
pars_obj=pass_testbench(sim_temp_dir,sim_pattern_dir,valid_pattern, ready_pattern, nb_frames,None)
sim=sim_command_pipeline(pars_obj)
tb=traceSignals(sim)
if (sim_time is None):
sim.run_sim()
else:
sim.run_sim(sim_time)
print("Simulation finished.................................")
print("Checking Simulation results.................................")
check_simulation_results(pars_obj)
os.chdir(cwd)
def _getDut(self, func, **kwargs):
''' Returns a simulation instance of func.
Uses the simulator specified by self._simulator.
Enables traces if self._trace is True
func - MyHDL function to be simulated
kwargs - dict of func interface assignments: for signals and parameters
'''
if self._simulator=="myhdl":
if not self._trace:
sim_dut = func(**kwargs)
else:
sim_dut = traceSignals(func, **kwargs)
else:
sim_dut = self._getCosimulation(func, **kwargs)
return sim_dut
def simulate(sim_temp_dir, sim_pattern_dir, valid_pattern, ready_pattern, nb_frames,sim_time=None):
print("Start Myhdl Simulation....................................")
cwd=os.getcwd()
os.chdir(sim_temp_dir)
inst.sim_defaults(sim_temp_dir)
pars_obj=pass_testbench(sim_temp_dir,sim_pattern_dir,valid_pattern, ready_pattern, nb_frames,None)
tb=traceSignals(sim_streaming_simple_modsub,pars_obj)
sim=Simulation(tb)
if (sim_time is None):
sim.run()
else:
sim.run(sim_time)
print("Simulation finished.................................")
print("Checking Simulation results.................................")
check_simulation_results(pars_obj)
os.chdir(cwd)
def test_mem():
def mem_test():
clk = Signal(bool(0))
rnw = Signal(bool(1))
di = Signal(intbv(0)[WIDTH:])
do = Signal(intbv(0)[WIDTH:])
a = Signal(intbv(0)[WIDTH:])
mem_inst = mem(do, di, a, rnw, clk, width=WIDTH, depth=DEPTH)
DELAY = delay(PERIOD // 2)
@always(DELAY)
def clkgen():
clk.next = not clk
@instance
def monitor():
while True:
print "%d MEM[%s] do %s di %s" % (rnw, BIN(a), BIN(do), BIN(di))
yield DELAY
@instance
def stimulus():
def write(byte, adr):
a.next = adr
di.next = byte
yield clk.posedge
rnw.next = 0
yield clk.posedge
rnw.next = 1
yield clk.posedge
for step in range(STEPS):
yield write(step << 4, step)
raise StopSimulation
return mem_inst, clkgen, monitor, stimulus
tb = traceSignals(mem_test)
sim = Simulation(tb)
sim.run()
def simulate_rx(self, stimulus, whitebox, **kwargs):
"""Acturally run the cosimulation with iverilog.
:param stimulus: A callable that returns the cosim object.
:param whitebox: A whitebox peripheral object.
:param record_tx: Record the passed in number of valid samples.
:param auto_stop: Raise ``StopSimulation`` when the correct number of samples have been recorded.
:param sample_rate: Samples per second.
"""
self.sample_rate = kwargs.get('sample_rate', 10e6)
print "SAMPLE RATE IS", self.sample_rate
auto_stop = kwargs.get('auto_stop', False)
DAC2X_DURATION = int(1e9 / (self.sample_rate * 2))
DAC_DURATION = int(1e9 / self.sample_rate)
self.receive_started = False
self.rx_time = []
@instance
def dac2x_clock():
while True:
self.dac2x_clock.next = not self.dac2x_clock
yield delay(DAC2X_DURATION // 2)
@instance
def dac_clock():
while True:
self.dac_clock.next = not self.dac_clock
yield delay(DAC_DURATION // 2)
@always(self.dac_clock.posedge,
self.bus.presetn.negedge)
def rx_player():
if not self.bus.presetn:
self.rx_n = 0
elif self.rx_n == len(self.rx_i) and auto_stop:
raise StopSimulation
elif self.receive_started and self.rx_n < len(self.rx_i):
self.adc_idata.next = self.rx_i[self.rx_n]
self.adc_qdata.next = self.rx_q[self.rx_n]
self.rx_time.append(now())
self.rx_n = self.rx_n + 1
traced = traceSignals(whitebox)
ss = [dac_clock, dac2x_clock, stimulus, traced, rx_player]
s = Simulation(ss)
s.run()
def simulate_rx(self, stimulus, whitebox, **kwargs):
"""Acturally run the cosimulation with iverilog.
:param stimulus: A callable that returns the cosim object.
:param whitebox: A whitebox peripheral object.
:param record_tx: Record the passed in number of valid samples.
:param auto_stop: Raise ``StopSimulation`` when the correct number of samples have been recorded.
:param sample_rate: Samples per second.
"""
self.sample_rate = kwargs.get('sample_rate', 10e6)
print "SAMPLE RATE IS", self.sample_rate
auto_stop = kwargs.get('auto_stop', False)
DAC2X_DURATION = int(1e9 / (self.sample_rate * 2))
DAC_DURATION = int(1e9 / self.sample_rate)
self.receive_started = False
self.rx_time = []
@instance
def dac2x_clock():
while True:
self.dac2x_clock.next = not self.dac2x_clock
yield delay(DAC2X_DURATION // 2)
@instance
def dac_clock():
while True:
self.dac_clock.next = not self.dac_clock
yield delay(DAC_DURATION // 2)
@always(self.dac_clock.posedge, self.bus.presetn.negedge)
def rx_player():
if not self.bus.presetn:
self.rx_n = 0
elif self.rx_n == len(self.rx_i) and auto_stop:
raise StopSimulation
elif self.receive_started and self.rx_n < len(self.rx_i):
self.adc_idata.next = self.rx_i[self.rx_n]
self.adc_qdata.next = self.rx_q[self.rx_n]
self.rx_time.append(now())
self.rx_n = self.rx_n + 1
traced = traceSignals(whitebox)
ss = [dac_clock, dac2x_clock, stimulus, traced, rx_player]
s = Simulation(ss)
s.run()
def test_register_sync():
def register_test():
ce = Signal(bool(0))
clk = Signal(bool(0))
q = Signal(intbv(0))
d = Signal(intbv(0))
reg = register_sync(q, d, ce, clk)
DELAY = delay(PERIOD // 2)
@always(DELAY)
def clkgen():
clk.next = not clk
@always(clk.negedge)
def monitor():
print "CEv %d %s %s" % (ce, bin(q, 16), bin(d, 16))
@instance
def stimulus():
for step in range(10):
d.next = step
if step % 2 == 0:
ce.next = not ce
yield clk.negedge
if ce == 0:
assert q != d
if ce == 1:
assert q == d
raise StopSimulation
return reg, clkgen, monitor, stimulus
tb = traceSignals(register_test)
sim = Simulation(tb)
sim.run()
def sim():
from myhdl import Simulation, traceSignals
import sys
bus = WbSlaveInterface(addr_depth=4, data_width=16)
bus.CLK_I = Clk(50E6, False)
clk_inst = bus.CLK_I.gen()
test_inst = traceSignals(test, bus)
extra_inst = []
if 1:
reader_inst = reader(bus, 4, 123 * nsec)
extra_inst.append(reader_inst)
sim = Simulation(clk_inst, test_inst, extra_inst)
sim.run(5 * usec)
print
sys.stdout.flush()
def sim():
from myhdl import Simulation, traceSignals
import sys
bus = WbSlaveInterface(addr_depth = 4, data_width = 16)
bus.CLK_I = Clk(False, 50E6)
clk_inst = bus.CLK_I.gen()
test_inst = traceSignals(test, bus)
extra_inst = []
if 1:
reader_inst = reader(bus, 4, 123 * nsec)
extra_inst.append(reader_inst)
sim = Simulation(clk_inst, test_inst, extra_inst)
sim.run(5 * usec)
print
sys.stdout.flush()
def run(self):
# can now either generate or simulate/convert/generateTcl
if self.args.QsysGenerate and not self.args.ignoreQsys:
if self.args.verbose:
print('Generating {} for Qsys' .format(self.args.targetHDL))
# force std_logic_vectors instead of unsigned in Interface as Qsys wants this
myhdl.toVHDL.std_logic_ports = True
self.convert(self, 'vhdl') # override self.args.targetHDL as this is 'always'verilog?
# rename the entity and architecture identifiers to match the name given by Qsys
generate.updateEntity("{}" .format(self.modulename), self.args.QsysGenerate[1])
# delete existing target
target = "{}{}.vhd" .format(self.args.QsysGenerate[0], self.args.QsysGenerate[1])
if os.path.exists(target):
os.remove(target)
os.rename("{}.vhd".format(self.modulename), target)
else:
if self.args.verbose:
print('Simulate, Convert, Generate _hw.tcl')
if self.testbench:
# remove 'old' .vcd file
filename = self.testbench[1].__name__ + ".vcd"
if os.access(filename, os.F_OK):
os.unlink(filename)
# Run Simulation
testbench = myhdl.traceSignals(self.testbench[1], self)
sim = myhdl.Simulation(testbench)
sim.run(self.testbench[0])
if self.convert:
if self.args.targetHDL is not None:
self.convert(self, self.args.targetHDL)
else:
# do both languages
self.convert(self, 'vhdl')
self.convert(self, 'verilog')
if self.gentcl:
generate.writeHwTcl(self.generics, self.connectionpointlist, self.modulename,
version=self.gentcl[0],
author=self.gentcl[1],
group=self.gentcl[2])
def run_testbench(bench, timescale='1ns', args=None):
""" run (simulate) a testbench
The args need to be retrieved outside the testbench
else the test will fail with the pytest runner, if
no args are passed a default will be used
"""
if args is None:
args = argparse.Namespace(trace=False)
vcd = tb_clean_vcd(bench.__name__)
if args.trace:
traceSignals.timescale = timescale
traceSignals.name = vcd
gens = traceSignals(bench)
else:
gens = bench()
sim = Simulation(gens)
sim.run()
del gens
del sim
def run_testbench(bench, timescale='1ns', args=None):
""" run (simulate) a testbench
The args need to be retrieved outside the testbench
else the test will fail with the pytest runner, if
no args are passed a default will be used
"""
if args is None:
args = argparse.Namespace(trace=False)
vcd = tb_clean_vcd(bench.__name__)
if args.trace:
traceSignals.timescale = timescale
traceSignals.name = vcd
gens = traceSignals(bench)
else:
gens = bench()
sim = Simulation(gens)
sim.run()
del gens
del sim
def run_sim(bench, time_steps=None, trace=False, **kwargs):
try:
M = len(bench)
benches = tuple(bench)
except TypeError:
M = 1
benches = (bench, )
b = []
if trace:
for i in range(M):
b.append(traceSignals(benches[i]))
else:
for i in range(M):
b.append(benches[i](**kwargs))
if M == 1:
s = Simulation(b[0])
else:
s = Simulation(tuple(b))
s.run(time_steps)
def testBench(args):
global DEBUG
DEBUG = args.debug
data_mem = load_data_memory(args.data) if args.data else None
program = args.program
Clk = Signal(intbv(0)[1:]) # internal clock
clk_driver = clock_driver(Clk, 1)
if args.vcd:
datapath_i = traceSignals(dlx, Clk, program=program, data_mem=data_mem) # () #toVHDL(datapath)
elif args.debug:
datapath_i = dlx(Clk, program=program, data_mem=data_mem)
elif args.to_vhdl:
toVHDL(dlx, Clk, program=program, data_mem=data_mem)
elif args.to_verilog:
toVerilog(dlx, Clk, program=program, data_mem=data_mem)
return instances()
def test_simulate(self):
import myhdl
duration = 1
def _sim():
bus = Apb3Bus(duration=duration)
bus_presetn = bus.presetn
bus_pclk = bus.pclk
bus_paddr = bus.paddr
bus_psel = bus.psel
bus_penable = bus.penable
bus_pwrite = bus.pwrite
bus_pwdata = bus.pwdata
bus_pready = bus.pready
bus_prdata = bus.prdata
bus_pslverr = bus.pslverr
status_led = Signal(bool(False))
slave = apb3_simple_slave(bus, status_led)
@myhdl.instance
def __sim():
yield bus.reset()
assert not status_led
yield bus.transmit(0x40, 0x0001)
assert status_led
yield bus.receive(0x40)
assert bus.rdata == 0x0001
assert not status_led
yield bus.receive(0x40)
assert bus.rdata == 0x0002
assert status_led
raise StopSimulation
return __sim, slave
s = myhdl.Simulation(myhdl.traceSignals(_sim))
s.run()
def run_IM_cosim():
# Initiate signals
MAX_TIME = 1000000
infile = INDEX_256
clock = Signal(0)
address = Signal(intbv(0, 0, 2**32), delay=10)
pyData = Signal(intbv(0, 0, 2**32))
vData = Signal(intbv(0, 0, 2**32))
# Build driver instances
clock_driver = clock_generator(clock, period=20)
addr_driver = random_signal(clock, address, seed=1)
py_cosim = traceSignals(py_im(clock, address, pyData, infile))
v_cosim = v_im(clock, address, vData, infile)
read_test = match_test_report(clock,
vData,
pyData,
a_name="v:",
b_name="py:")
sim = Simulation(instances())
sim.run(MAX_TIME)
def test_simulate(self):
import myhdl
duration=1
def _sim():
bus = Apb3Bus(duration=duration)
bus_presetn = bus.presetn
bus_pclk = bus.pclk
bus_paddr = bus.paddr
bus_psel = bus.psel
bus_penable = bus.penable
bus_pwrite = bus.pwrite
bus_pwdata = bus.pwdata
bus_pready = bus.pready
bus_prdata = bus.prdata
bus_pslverr = bus.pslverr
status_led = Signal(bool(False))
slave = apb3_simple_slave(bus, status_led)
@myhdl.instance
def __sim():
yield bus.reset()
assert not status_led
yield bus.transmit(0x40, 0x0001)
assert status_led
yield bus.receive(0x40)
assert bus.rdata == 0x0001
assert not status_led
yield bus.receive(0x40)
assert bus.rdata == 0x0002
assert status_led
raise StopSimulation
return __sim, slave
s = myhdl.Simulation(myhdl.traceSignals(_sim))
s.run()
def sim():
from myhdl import Simulation, traceSignals, ResetSignal
from rhea.system import Clock
import sys
clk = Clock(0, 50E6)
rst = ResetSignal(0, active=1, async=0)
spi_bus = SpiInterface()
clk_inst = clk.gen()
@instance
def rst_inst():
rst.next = 1
yield (delay(100))
rst.next = 0
test_inst = traceSignals(top, clk, rst, spi_bus)
sim = Simulation(clk_inst, rst_inst, test_inst)
sim.run(10000)
print
sys.stdout.flush()
def sim():
from myhdl import Simulation, traceSignals, instance, delay
insts, gen, args = setup()
wb_bus = args[1]
insts.append(traceSignals(gen, *args))
cs = (1<<1)
cpol = 0
cpha = 0
pulse = 1
@instance
def test():
yield delay(149 * nsec)
yield(wb_read(wb_bus, 0))
yield(delay(29 * nsec))
yield(wb_write(wb_bus, 0, 0x0000025))
yield(delay(29 * nsec))
yield(wb_read(wb_bus, 0))
yield(delay(29 * nsec))
yield(wb_write(wb_bus, 1,
6 | (cpha<<8) | (cpol<<9) | (pulse<<10) | (cs<<16)))
while 1:
yield(delay(29 * nsec))
yield(wb_read(wb_bus, 1))
insts.append(test)
sim = Simulation(insts)
sim.run(1500 * nsec)
print
sys.stdout.flush()
def stimulate_VCD():
tb = traceSignals(testBench_FA)
sim = Simulation(tb)
sim.run()
