def generate(top):
from nmigen_boards.icestick import ICEStickPlatform
platform = ICEStickPlatform()
platform.add_resources([
Resource(
'sound_out',
0,
Subsignal('pin', Pins('3', conn=('j', 1), dir='o')),
)
])
platform.build(top, do_program=args.program or args.interactive)
def __init__(self):
lvcmos = self.lvcmos
# Create resources for each LED header
for jidx, pins in enumerate(self.leds):
self.resources += [
Resource("led_rgb", jidx,
Subsignal("r0", Pins(pins[0], dir="o"), lvcmos),
Subsignal("g0", Pins(pins[1], dir="o"), lvcmos),
Subsignal("b0", Pins(pins[2], dir="o"), lvcmos),
Subsignal("r1", Pins(pins[3], dir="o"), lvcmos),
Subsignal("g1", Pins(pins[4], dir="o"), lvcmos),
Subsignal("b1", Pins(pins[5], dir="o"), lvcmos))
]
# Create resources for each unknown pin
for pin in self.outputs:
self.resources += [Resource(pin, 0, Pins(pin, dir="o"), lvcmos)]
for pin in self.inputs:
self.resources += [Resource(pin, 0, Pins(pin, dir="i"), lvcmos)]
for pin in self.bidis:
self.resources += [Resource(pin, 0, Pins(pin, dir="io"), lvcmos)]
super().__init__()
class TinyBoneless(TinyFPGABXPlatform):
resources = TinyFPGABXPlatform.resources + [
# FTDI link for now
Resource(
"uart",
0,
Subsignal("tx", Pins("19", conn=("gpio", 0), dir="o")),
Subsignal("rx", Pins("20", conn=("gpio", 0), dir="i")),
Subsignal("dtr", Pins("21", conn=("gpio", 0), dir="i")),
),
*LEDResources("blinky",
pins="J1 H2 H9 D9",
attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
]
user_flash = (0x50000, 0xFBFFF)
class PaintController(TinyFPGABXPlatform):
resources = TinyFPGABXPlatform.resources + [
Resource(
"spi",
0,
Subsignal("clk", Pins("4", conn=("gpio", 0), dir="i")),
Subsignal("ss", Pins("5", conn=("gpio", 0), dir="i")),
Subsignal("miso", Pins("6", conn=("gpio", 0), dir="o")),
Subsignal("mosi", Pins("7", conn=("gpio", 0), dir="i")),
),
Resource(
"dispenser",
0,
Subsignal("stepper", Pins("8", conn=("gpio", 0), dir="o")),
Subsignal("limit_top", Pins("9", conn=("gpio", 0), dir="i")),
Subsignal("limit_bottom", Pins("10", conn=("gpio", 0), dir="i")),
),
Resource(
"dispenser",
1,
Subsignal("stepper", Pins("11", conn=("gpio", 0), dir="o")),
Subsignal("limit_top", Pins("12", conn=("gpio", 0), dir="i")),
Subsignal("limit_bottom", Pins("13", conn=("gpio", 0), dir="i")),
),
Resource(
"dispenser",
2,
Subsignal("stepper", Pins("14", conn=("gpio", 0), dir="o")),
Subsignal("limit_top", Pins("15", conn=("gpio", 0), dir="i")),
Subsignal("limit_bottom", Pins("16", conn=("gpio", 0), dir="i")),
),
Resource(
"dispenser",
3,
Subsignal("stepper", Pins("17", conn=("gpio", 0), dir="o")),
Subsignal("limit_top", Pins("18", conn=("gpio", 0), dir="i")),
Subsignal("limit_bottom", Pins("19", conn=("gpio", 0), dir="i")),
),
Resource(
"dispenser",
4,
Subsignal("stepper", Pins("20", conn=("gpio", 0), dir="o")),
Subsignal("limit_top", Pins("21", conn=("gpio", 0), dir="i")),
Subsignal("limit_bottom", Pins("22", conn=("gpio", 0), dir="i")),
),
Resource(
"motor_enable",
0,
Pins("23", conn=("gpio", 0), dir="o"),
)
]
def ULPIResource(name,
data_sites,
clk_site,
dir_site,
nxt_site,
stp_site,
reset_site,
extras=()):
""" Generates a set of resources for a ULPI-connected USB PHY. """
return Resource(
name, 0, Subsignal("data", Pins(data_sites, dir="io")),
Subsignal("clk", Pins(clk_site, dir="i"), Attrs(PULLDOWN="TRUE"),
Clock(60e6)), Subsignal("dir", Pins(dir_site, dir="i")),
Subsignal("nxt", Pins(nxt_site, dir="i")),
Subsignal("stp", Pins(stp_site, dir="o")),
Subsignal("rst", PinsN(reset_site, dir="o")), Attrs(SLEW="FAST"))
def elaborate(self, platform):
m = Module()
resources = [
Resource("wishbone", 0,
Subsignal("adr", Pins("ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7"
" ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15"
" ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23"
" ADDR24 ADDR25 ADDR26 ADDR27 ADDR28 ADDR29 ADDR30 ADDR31", dir="i")),
Subsignal("dat_r", Pins("DATR0 DATR1 DATR2 DATR3 DATR4 DATR5 DATR6 DATR7"
" DATR8 DATR9 DATR10 DATR11 DATR12 DATR13 DATR14 DATR15"
" DATR16 DATR17 DATR18 DATR19 DATR20 DATR21 DATR22 DATR23"
" DATR24 DATR25 DATR26 DATR27 DATR28 DATR29 DATR30 DATR31", dir="o")),
Subsignal("dat_w", Pins("DATW0 DATW1 DATW2 DATW3 DATW4 DATW5 DATW6 DATW7"
" DATW8 DATW9 DATW10 DATW11 DATW12 DATW13 DATW14 DATW15"
" DATW16 DATW17 DATW18 DATW19 DATW20 DATW21 DATW22 DATW23"
" DATW24 DATW25 DATW26 DATW27 DATW28 DATW29 DATW30 DATW31", dir="i")),
Subsignal("cyc", Pins("CYC", dir="i")),
Subsignal("stb", Pins("STB", dir="i")),
Subsignal("sel", Pins("SEL0 SEL1 SEL2 SEL3", dir="i")),
Subsignal("ack", Pins("ACK", dir="o")),
Subsignal("we", Pins("WE", dir="i"))),
]
platform.add_resources(resources)
m.submodules.sysclk = self.crg
m.submodules.decoder = self._decoder
m.submodules.ddrphy = self.ddrphy
m.submodules.dramcore = self.dramcore
m.submodules.drambone = self.drambone
ext_bus = platform.request("wishbone", 0)
m.d.comb += [
self._decoder.bus.adr.eq(ext_bus.adr.i),
self._decoder.bus.dat_w.eq(ext_bus.dat_w.i),
ext_bus.dat_r.o.eq(self._decoder.bus.dat_r),
self._decoder.bus.cyc.eq(ext_bus.cyc.i),
self._decoder.bus.stb.eq(ext_bus.stb.i),
self._decoder.bus.sel.eq(ext_bus.sel.i),
ext_bus.ack.o.eq(self._decoder.bus.ack),
self._decoder.bus.we.eq(ext_bus.we.i),
]
return m
def load():
from boards.qmtech_wukong import Platform as wukong
wukong.resources += [
Resource("clk_n", 0, Pins("AB13", dir="i")),
Resource("clk_p", 0, Pins("AA13", dir="i")),
Resource("tx_n", 0, Pins("AD10")),
Resource("tx_p", 0, Pins("AC10")),
Resource("rx_n", 0, Pins("AD12")),
Resource("rx_p", 0, Pins("AC12"))
]
return (wukong, XilinxGTPSerdes)
def ULPIResource(name,
data_sites,
clk_site,
dir_site,
nxt_site,
stp_site,
reset_site,
extras=(),
attrs=None):
""" Generates a set of resources for a ULPI-connected USB PHY. """
attrs = Attrs() if attrs is None else attrs
return Resource(name, 0, Subsignal("data", Pins(data_sites, dir="io")),
Subsignal("clk", Pins(clk_site, dir="i"), Clock(60e6)),
Subsignal("dir", Pins(dir_site, dir="i")),
Subsignal("nxt", Pins(nxt_site, dir="i")),
Subsignal("stp", Pins(stp_site, dir="o")),
Subsignal("rst", Pins(reset_site, dir="o")), attrs)
def build(TheFirmware, mem_size=4096, sim=False, detail=False):
# for programming from a firmware file
if detail:
print("Testing Spork")
# TODO abstract this plaform set
platform = TinyFPGABXPlatform()
# FTDI on the tinybx
platform.add_resources([
UARTResource(0,
rx="A8",
tx="B8",
attrs=Attrs(IO_STANDARD="SB_LVCMOS", PULLUP=1)),
Resource("reset_pin", 0, Pins("A9", dir="i"),
Attrs(IO_STANDARD="SB_LVCMOS")),
# *ButtonResources(pins="10", invert=True, attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
*LEDResources("blinky",
pins="J1 H2 H9 D9",
attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
])
# Spork it up
spork = TestSpork(platform, uart_speed=115200, mem_size=mem_size, sim=sim)
# Build the firmware
spork.build()
if detail:
print(spork.cpu.map.show())
f = TheFirmware(spork.cpu.map, start_window=mem_size)
spork.fw = f
if detail:
f.show()
# Sporkify it !
code = f.code()
spork.cpu.firmware(code)
if detail:
print(f.hex())
spork.hex_blob = f.hex()
return spork
class BetaRFWPlatform(LatticeMachXO2Platform):
device = "LCMXO2-2000HC"
package = "TG100"
speed = "6"
resources = [
Resource(
"pic_io",
0,
Subsignal("ss", Pins("27", dir="io"),
Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP", DRIVE="4")),
Subsignal("sck", Pins("31", dir="io"),
Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP", DRIVE="4")),
Subsignal("sdo", Pins("32", dir="io"),
Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP", DRIVE="4")),
Subsignal("pb22b", Pins("47", dir="io"),
Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP", DRIVE="4")),
Subsignal("sn", Pins("48", dir="io"),
Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP", DRIVE="4")),
Subsignal("sdi", Pins("49", dir="io"),
Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP", DRIVE="4")),
Subsignal("done", Pins("76", dir="io"),
Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP", DRIVE="4")),
Subsignal("initn", Pins("77", dir="io"),
Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP", DRIVE="4")),
)
]
connectors = []
def __init__(self):
super().__init__()
add_plugin_connector(
self,
"north",
gpio=["83", "78", "74", "75", "71", "70", "69", "68"])
add_plugin_connector(
self, "south", gpio=["1", "2", "98", "99", "96", "97", "84", "87"])
def build(top):
from nmigen_boards.icestick import ICEStickPlatform
platform = ICEStickPlatform()
platform.add_resources([
Resource("spi", 0,
Subsignal("mosi", Pins('3', conn=('j', 1), dir='i')),
Subsignal("sclk", Pins('4', conn=('j', 1), dir='i')),
Subsignal("ssel", Pins('5', conn=('j', 1), dir='i')),
)
])
conn = platform.request('spi')
spi = top.submodules.spi
top.d.comb += [
spi.i_mosi.eq(conn.mosi),
spi.i_sclk.eq(conn.sclk),
spi.i_ssel.eq(conn.ssel),
platform.request('led', 4).eq(spi.o_done),
platform.request('led', 0).eq(spi.o_data[0]),
]
platform.build(top, do_program = False)
class BB(TinyFPGABXPlatform):
resources = TinyFPGABXPlatform.resources + [
# FTDI link back to pc
Resource(
"serial",
0,
Subsignal("tx", Pins("19", conn=("gpio", 0), dir="o")),
Subsignal("rx", Pins("20", conn=("gpio", 0), dir="i")),
),
Resource("user_led", 1, Pins("12", conn=("gpio", 0), dir="o")),
Resource("user_led", 2, Pins("13", conn=("gpio", 0), dir="o")),
Resource("user_led", 3, Pins("14", conn=("gpio", 0), dir="o")),
Resource("user_led", 4, Pins("15", conn=("gpio", 0), dir="o")),
Resource("pwm", 0, Pins("5", conn=("gpio", 0), dir="o")),
]
clock = "clk16"
def freq(self):
clk = self.lookup(self.clock)
return clk.clock.frequency
class FMCWRadar(Xilinx7SeriesPlatform):
"""
"""
device = "XC7A15T"
package = "FTG256"
speed = "1"
resources = [
Resource(
"clk40",
0,
Pins("N11", dir="i"),
Clock(40e6),
Attrs(IOSTANDARD="LVCMOS33"),
),
Resource(
"ft_data_io",
0,
Pins("F15 G16 G15 F14 E16 E15 D16 D15", dir="io"),
Attrs(IOSTANDARD="LVCMOS33"),
),
Resource(
"ft_clkout_i",
0,
Pins("A15", dir="i"),
Clock(60e6),
Attrs(IOSTANDARD="LVCMOS33"),
),
Resource(
"ft_wr_n_o", 0, Pins("A14", dir="o"), Attrs(IOSTANDARD="LVCMOS33")
),
Resource(
"ft_rd_n_o", 0, Pins("B14", dir="o"), Attrs(IOSTANDARD="LVCMOS33")
),
Resource(
"ft_rxf_n_i", 0, Pins("B16", dir="i"), Attrs(IOSTANDARD="LVCMOS33")
),
Resource(
"ft_txe_n_i", 0, Pins("B15", dir="i"), Attrs(IOSTANDARD="LVCMOS33")
),
Resource(
"ft_siwua_n_o",
0,
Pins("A13", dir="o"),
Attrs(IOSTANDARD="LVCMOS33"),
),
Resource(
"ft_oe_n_o", 0, Pins("A12", dir="o"), Attrs(IOSTANDARD="LVCMOS33")
),
Resource(
"ft_suspend_n_i",
0,
Pins("C16", dir="i"),
Attrs(IOSTANDARD="LVCMOS33"),
),
Resource(
"adc_d_i",
0,
Pins("L2 K2 K1 J3 H1 H2 H3 G2 G1 F2 E1 E2", dir="i"),
Attrs(IOSTANDARD="LVCMOS33"),
),
Resource(
"adc_oe_o",
0,
Pins("B2 P1", dir="o"),
Attrs(IOSTANDARD="LVCMOS33"),
),
Resource(
"adc_shdn_o",
0,
Pins("B1 N2", dir="o"),
Attrs(IOSTANDARD="LVCMOS33"),
),
Resource("led", 0, Pins("D1", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource(
"ext1",
0,
Pins("C11 B10 A9 C12 B9 A8", dir="o"),
Attrs(IOSTANDARD="LVCMOS33"),
),
Resource(
"pa_en_n_o", 0, Pins("T2", dir="o"), Attrs(IOSTANDARD="LVCMOS33")
),
Resource(
"mix_en_n_o", 0, Pins("J4", dir="o"), Attrs(IOSTANDARD="LVCMOS33")
),
]
connectors = []
default_clk = "clk40"
def toolchain_program(self, products, name):
# bitstream = products.get("{}.bin".format(name))
os.system("openocd -f interface.cfg -f program_fpga.cfg")
m.d.serdes += to_oserdes.eq(to_oserdes + 1)
with m.If(from_iserdes == (last_received + 1)[0:8]):
m.d.serdes += success_cnt.eq(success_cnt + 1)
with m.Else():
m.d.serdes += error_cnt.eq(error_cnt + 1)
m.d.serdes += last_received.eq(from_iserdes)
m.d.comb += last_current_out.eq(
Cat(last_received, from_iserdes, to_oserdes))
return m
if __name__ == "__main__":
with cli(Top,
runs_on=(MicroR2Platform, ),
possible_socs=(ZynqSocPlatform, )) as platform:
platform.add_resources([
Resource(
"loopback",
0,
# high speed serial lanes
Subsignal("tx",
DiffPairs("1", "7", dir='o', conn=("pmod", "south")),
Attrs(IOSTANDARD="LVDS_25")),
Subsignal("rx",
DiffPairs("8", "2", dir='i', conn=("pmod", "south")),
Attrs(IOSTANDARD="LVDS_25")),
)
])
class GbCartPlatform(IntelPlatform):
device = "5M40Z"
package = "E64"
speed = "C5"
resources = [
Resource(
"cart_rst",
0,
Pins("29", dir="i", invert=True),
Attrs(io_standard="3.3V SCHMITT TRIGGER INPUT"),
),
Resource(
"cart_addr",
0,
Pins("55 54 24 25 26 27 28 30 31 32 21 20 49 53 52 56", dir="i"),
Attrs(io_standard="3.3V SCHMITT TRIGGER INPUT",
enable_bus_hold_circuitry="ON"),
),
Resource(
"cart_data",
0,
Pins("58 59 60 61 62 63 64 1", dir="i"),
Attrs(io_standard="3.3V SCHMITT TRIGGER INPUT",
enable_bus_hold_circuitry="ON"),
),
Resource(
"cart_rd",
0,
Pins("33", dir="i", invert=True),
Attrs(io_standard="3.3V SCHMITT TRIGGER INPUT"),
),
Resource(
"cart_wr",
0,
Pins("44", dir="i", invert=True),
Attrs(io_standard="3.3V SCHMITT TRIGGER INPUT"),
),
Resource(
"cart_cs",
0,
Pins("47", dir="i", invert=True),
Attrs(io_standard="3.3V SCHMITT TRIGGER INPUT"),
),
Resource(
"cart_phi",
0,
Pins("48", dir="i"),
Attrs(io_standard="3.3V SCHMITT TRIGGER INPUT",
enable_bus_hold_circuitry="ON"),
),
Resource(
"rom_wr",
0,
Pins("10", dir="i", invert=True),
Attrs(io_standard="3.3V SCHMITT TRIGGER INPUT"),
),
Resource("data_dir", 0, Pins("51", dir="o"),
Attrs(io_standard="3.3-V LVCMOS")),
Resource(
"cart_oe",
0,
Pins("46", dir="o", invert=True),
Attrs(io_standard="3.3-V LVCMOS"),
),
Resource(
"ram_cs",
0,
Pins("35", dir="o", invert=True),
Attrs(io_standard="3.3-V LVCMOS"),
),
Resource(
"ram_bank",
0,
Pins("36 37 38 34", dir="o"),
Attrs(io_standard="3.3-V LVCMOS"),
),
Resource(
"rom_bank",
0,
Pins("5 4 3 2 13 11 7 9 12", dir="o"),
Attrs(io_standard="3.3-V LVCMOS"),
),
]
connectors = []
file_templates = {
**IntelPlatform.file_templates,
"{{name}}.qsf":
IntelPlatform.file_templates["{{name}}.qsf"] + r"""
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT HIGH
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH BUS-HOLD"
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE POWER"
set_global_assignment -name AUTO_RESOURCE_SHARING ON
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
""",
"{{name}}.sdc":
IntelPlatform.file_templates["{{name}}.sdc"] + r"""
create_clock -name gb_clk -period 120 -waveform {10 110}
create_clock -name ramg_clk -period 120 -waveform {10 110} [get_nets {gb_cart|mbc|ramg_clk}]
create_clock -name romb0_clk -period 120 -waveform {10 110} [get_nets {gb_cart|mbc|romb0_clk}]
create_clock -name romb1_clk -period 120 -waveform {10 110} [get_nets {gb_cart|mbc|romb1_clk}]
create_clock -name ramb_clk -period 120 -waveform {10 110} [get_nets {gb_cart|mbc|ramb_clk}]
set_input_delay -clock { gb_clk } 20 [get_ports {cart_rd_* cart_wr_* cart_cs_* cart_addr_* cart_data_* rom_wr_*}]
set_output_delay -clock { gb_clk } 20 [get_ports {ram_bank_* rom_bank_* data_dir_* ram_cs_* cart_oe_*}]
set_false_path -from [get_ports {cart_rst_*}] -to *
""",
}
def get_input(self, pin, port, attrs, invert):
self._check_feature("single-ended input",
pin,
attrs,
valid_xdrs=(0, 1),
valid_attrs=True)
m = Module()
i = self._get_ireg(m, pin, invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name,
bit)] = Instance("alt_inbuf",
i_i=port.io[bit],
o_o=i[bit])
return m
def get_output(self, pin, port, attrs, invert):
self._check_feature("single-ended output",
pin,
attrs,
valid_xdrs=(0, 1),
valid_attrs=True)
m = Module()
o = self._get_oreg(m, pin, invert)
for bit in range(pin.width):
m.submodules["{}_{}".format(pin.name,
bit)] = Instance("alt_outbuf",
i_i=o[bit],
o_o=port.io[bit])
return m
# uart Rx -> ext Tx
# ext Rx -> uart Tx
m.d.comb += [
ext_pins.tx.eq(uart_pins.rx),
uart_pins.tx.eq(ext_pins.rx),
]
return m
if __name__ == '__main__':
plat = ICEBreakerPlatform()
plat.add_resources(plat.break_off_pmod)
# The external IO pins to use
ext_io = [
Resource(
'ext_io',
0,
# External Input
Subsignal('rx', Pins('4', dir='i', conn=('pmod', 0)),
Attrs(IO_STANDARD="LVCMOS33", PULLUP=1)),
# External Output
Subsignal('tx', Pins('3', dir='o', conn=('pmod', 0)),
Attrs(IO_STANDARD="LVCMOS33", PULLUP=1)),
),
]
plat.add_resources(ext_io)
plat.build(Top(pins='ext_io'), do_program=True)
class OrangeCrabR0D2(OrangeCrabPlatform, LUNAPlatform):
""" Board description for OrangeCrab r0.2. """
name = "OrangeCrab r0.2"
#
# I/O resources.
#
resources = [
# System clock.
Resource("clk_48MHz", 0, Pins("A9"), Attrs(IO_TYPE="LVCMOS33"),
Clock(48e6)),
# Self-reset.
Resource("rst_n", 0, Pins("V17"), Attrs(IO_TYPE="LVCMOS33")),
# Buttons.
Resource("user_button", 0, Pins("J17"), Attrs(IO_TYPE="SSTL135_I")),
# LEDs.
Resource(
"rgb_led",
0,
Subsignal("r", Pins("K4", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Subsignal("g", Pins("M3", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Subsignal("b", Pins("J3", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
),
# Create aliases for our LEDs with standard naming.
Resource("led", 0, Pins("K4", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 1, Pins("M3", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 2, Pins("J3", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
# RAM.
Resource(
"ddram", 0,
Subsignal(
"a", Pins("C4 D2 D3 A3 A4 D4 C3 B2"
"B1 D1 A7 C2 B6 C1 A2 C7"),
Attrs(IO_TYPE="SSTL135_I")),
Subsignal(
"ba",
Pins("D6 B7 A6"),
Attrs(IO_TYPE="SSTL135_I"),
), Subsignal("ras_n", Pins("C12"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("cas_n", Pins("D13"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("we_n", Pins("B12"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("cs_n", Pins("A12"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("dm", Pins("D16 G16"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal(
"dq",
Pins("C17 D15 B17 C16 A15 B13 A17 A13"
"F17 F16 G15 F15 J16 C18 H16 F18"),
Attrs(IO_TYPE="SSTL135_I"), Attrs(TERMINATION="75")),
Subsignal("dqs_p", Pins("B15 G18"), Attrs(IO_TYPE="SSTL135D_I"),
Attrs(TERMINATION="OFF"), Attrs(DIFFRESISTOR="100")),
Subsignal("clk_p", Pins("J18"), Attrs(IO_TYPE="SSTL135D_I")),
Subsignal("cke", Pins("D18"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("odt", Pins("C13"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("reset_n", Pins("L18"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("vccio", Pins("K16 D17 K15 K17 B18 C6"),
Attrs(IO_TYPE="SSTL135_II")),
Subsignal("gnd", Pins("L15 L16"), Attrs(IO_TYPE="SSTL135_II")),
Attrs(SLEWRATE="FAST")),
# USB Connector.
Resource("usb", 0, Subsignal("d_p", Pins("N1", dir="io")),
Subsignal("d_n", Pins("M2", dir="io")),
Subsignal("pullup", Pins("N2", dir="o")),
Attrs(IO_TYPE="LVCMOS33")),
# Onboard flash.
Resource(
"spiflash4x",
0,
Subsignal("cs_n", Pins("U17"), Attrs(IO_TYPE="LVCMOS33")),
#Subsignal("clk", Pins("U16"), Attrs(IO_TYPE="LVCMOS33")),
Subsignal("dq", Pins("U18 T18 R18 N18"),
Attrs(IO_TYPE="LVCMOS33")),
),
Resource(
"spiflash",
0,
Subsignal("cs_n", Pins("U17"), Attrs(IO_TYPE="LVCMOS33")),
#Subsignal("clk", Pins("U16"), Attrs(IO_TYPE="LVCMOS33")), # Note: CLK is bound using USRMCLK block
Subsignal("miso", Pins("T18"), Attrs(IO_TYPE="LVCMOS33")),
Subsignal("mosi", Pins("U18"), Attrs(IO_TYPE="LVCMOS33")),
Subsignal("wp", Pins("R18"), Attrs(IO_TYPE="LVCMOS33")),
Subsignal("hold", Pins("N18"), Attrs(IO_TYPE="LVCMOS33")),
),
# SD Card.
Resource(
"spisdcard",
0,
Subsignal("clk", Pins("K1")),
Subsignal("mosi", Pins("K2"), Attrs(PULLMODE="UP")),
Subsignal("cs_n", Pins("M1"), Attrs(PULLMODE="UP")),
Subsignal("miso", Pins("J1"), Attrs(PULLMODE="UP")),
Attrs(SLEW="FAST"),
Attrs(IO_TYPE="LVCMOS33"),
),
# User I/O
Resource("user_io", 0, Pins("N17")),
Resource("user_io", 1, Pins("M18")),
Resource("user_io", 2, Pins("C10")),
Resource("user_io", 3, Pins("C9")),
# 4
Resource("user_io", 5, Pins("B10")),
Resource("user_io", 6, Pins("B9")),
# 7
# 8
Resource("user_io", 9, Pins("C8")),
Resource("user_io", 10, Pins("B8")),
Resource("user_io", 11, Pins("A8")),
Resource("user_io", 12, Pins("H2")),
Resource("user_io", 13, Pins("J2")),
Resource("user_io", 14, Pins("N15")),
Resource("user_io", 15, Pins("R17")),
Resource("user_io", 16, Pins("N16")),
# 17
Resource("user_io", 18, Pins("L4")),
Resource("user_io", 19, Pins("N3")),
Resource("user_io", 20, Pins("N4")),
Resource("user_io", 21, Pins("H4")),
Resource("user_io", 22, Pins("G4")),
Resource("user_io", 23, Pins("T17")),
]
connectors = [
Connector(
"GPIO", 0,
"N17 M18 C10 C9 - B10 B9 - - C8 B8 A8 H2 J2 N15 R17 N16 - L4 N3 N4 H4 G4 T17"
)
]
class Basys3Platform(Xilinx7SeriesPlatform):
device = "xc7a35t"
package = "cpg236"
speed = "1"
default_clk = "CLK100"
# J connectors are layed out looking at the connector head-on [6-1],[12-7]
# J[A(0), B(1), C(2), XADC(3)]
connectors = [
# JA
Connector("J", 0, " - - G2 J2 L2 J1 "
" - - G3 H2 K2 H1 "),
# JB
Connector("J", 1, " - - B16 B15 A16 A14 "
" - - C16 C15 A17 A15 "),
# JC
Connector("J", 2, " - - P18 N17 M18 K17 "
" - - R18 P17 M19 L17 "),
# JXADC
Connector("J", 3, " - - N2 M2 L3 J3 "
" - - N1 M1 M3 K3 "),
]
resources = [
# Integrated 100MHz clock
Resource("CLK100", 0, Pins("W5", dir="i"), Clock(100e6),
Attrs(IOSTANDARD="LVCMOS33")),
# Onboard LEDs: LD[0-15]
Resource("LD", 0, Pins("U16", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 1, Pins("E19", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 2, Pins("U19", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 3, Pins("V19", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 4, Pins("W18", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 5, Pins("U15", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 6, Pins("U14", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 7, Pins("V14", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 8, Pins("V13", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 9, Pins("V3", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 10, Pins("W3", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 11, Pins("U3", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 12, Pins("P3", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 13, Pins("N3", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 14, Pins("P1", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 15, Pins("L1", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
# Onboard switches: SW[0-15]
Resource("SW", 0, Pins("V17", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 1, Pins("V16", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 2, Pins("W16", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 3, Pins("W17", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 4, Pins("W15", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 5, Pins("V15", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 6, Pins("W14", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 7, Pins("W13", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 8, Pins("V2", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 9, Pins("T3", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 10, Pins("T2", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 11, Pins("R3", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 12, Pins("W2", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 13, Pins("U1", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 14, Pins("T1", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 15, Pins("R2", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
# Onboard buttons: BTN[L(0),R(1),U(2),D(3),C(4)]
Resource("BTN", 0, Pins("W19", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("BTN", 1, Pins("T17", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("BTN", 2, Pins("T18", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("BTN", 3, Pins("U17", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("BTN", 4, Pins("U18", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
# 7seg anode/cathodes: AN[0-3] C[A(0),B(1),C(2),D(3),E(4),F(5),G(6),P(7)]
Resource("7SEG", 0, Subsignal("AN0", Pins("U2", dir="o")),
Subsignal("AN1", Pins("U4", dir="o")),
Subsignal("AN2", Pins("V4", dir="o")),
Subsignal("AN3", Pins("W4", dir="o")),
Subsignal("CA", PinsN("W7", dir="o")),
Subsignal("CB", PinsN("W6", dir="o")),
Subsignal("CC", PinsN("U8", dir="o")),
Subsignal("CD", PinsN("V8", dir="o")),
Subsignal("CE", PinsN("U5", dir="o")),
Subsignal("CF", PinsN("V5", dir="o")),
Subsignal("CG", PinsN("U7", dir="o")),
Subsignal("CP", PinsN("V7", dir="o")),
Attrs(IOSTANDARD="LVCMOS33")),
# VGA port
Resource("VGA", 0, Subsignal("RED0", Pins("G19", dir="o")),
Subsignal("RED1", Pins("H19", dir="o")),
Subsignal("RED2", Pins("J19", dir="o")),
Subsignal("RED3", Pins("N19", dir="o")),
Subsignal("GRN0", Pins("J17", dir="o")),
Subsignal("GRN1", Pins("H17", dir="o")),
Subsignal("GRN2", Pins("G17", dir="o")),
Subsignal("GRN3", Pins("D17", dir="o")),
Subsignal("BLU0", Pins("N18", dir="o")),
Subsignal("BLU1", Pins("L18", dir="o")),
Subsignal("BLU2", Pins("K18", dir="o")),
Subsignal("BLU3", Pins("J18", dir="o")),
Subsignal("HSYNC", Pins("P19", dir="o")),
Subsignal("VSYNC", Pins("R19", dir="o")),
Attrs(IOSTANDARD="LVCMOS33")),
# JA GPIO
Resource("JA", 0, Subsignal("P1", Pins("J1")),
Subsignal("P2", Pins("L2")), Subsignal("P3", Pins("J2")),
Subsignal("P4", Pins("G2")), Subsignal("P7", Pins("H1")),
Subsignal("P8", Pins("K2")), Subsignal("P9", Pins("H2")),
Subsignal("P10", Pins("G3")), Attrs(IOSTANDARD="LVCMOS33")),
# JB GPIO
Resource("JB", 0, Subsignal("P1", Pins("A14")),
Subsignal("P2", Pins("A16")), Subsignal("P3", Pins("B15")),
Subsignal("P4", Pins("B16")), Subsignal("P7", Pins("A15")),
Subsignal("P8", Pins("A17")), Subsignal("P9", Pins("C15")),
Subsignal("P10", Pins("C16")), Attrs(IOSTANDARD="LVCMOS33")),
# JC GPIO
Resource("JC", 0, Subsignal("P1", Pins("K17")),
Subsignal("P2", Pins("M18")), Subsignal("P3", Pins("N17")),
Subsignal("P4", Pins("P18")), Subsignal("P7", Pins("L17")),
Subsignal("P8", Pins("M19")), Subsignal("P9", Pins("P17")),
Subsignal("P10", Pins("R18")), Attrs(IOSTANDARD="LVCMOS33")),
# JXADC GPIO
Resource("JXADC", 0, Subsignal("P1", Pins("J3")),
Subsignal("P2", Pins("L3")), Subsignal("P3", Pins("M2")),
Subsignal("P4", Pins("N2")), Subsignal("P7", Pins("K3")),
Subsignal("P8", Pins("M3")), Subsignal("P9", Pins("M1")),
Subsignal("P10", Pins("N1")), Attrs(IOSTANDARD="LVCMOS33")),
# Onboard SPI flash
*SPIFlashResources(0,
cs="K19",
clk="C11",
mosi="D18",
miso="D19",
wp="G18",
hold="F18",
attrs=Attrs(IOSTANDARD="LVCMOS33")),
]
def toolchain_program(self, products, name):
djtgcfg = os.environ.get("DJTGCFG", "djtgcfg")
with products.extract("{}.bit".format(name)) as bitstream_filename:
subprocess.run([
djtgcfg, "prog", "-d", "Basys3", "-i", "0", "-f",
bitstream_filename
],
check=True)
class SwitchPlatform(LatticeICE40Platform):
device = "iCE40HX8K"
package = "BG121"
resources = [
Resource("clk25", 0, Pins("B6", dir="i")),
Resource("user_led", 0, Pins("A11", dir="o")),
Resource("user_led", 1, Pins("A10", dir="o")),
Resource(
"uart",
0,
Subsignal("rx", Pins("A4", dir="i")),
Subsignal("tx", Pins("A3", dir="o")),
),
Resource(
"flash",
0,
Subsignal("sdi", Pins("K9", dir="o")),
Subsignal("sdo", Pins("J9", dir="i")),
Subsignal("sck", Pins("L10", dir="o")),
Subsignal("cs", Pins("K10", dir="o")),
Subsignal("io2", Pins("K11", dir="i")),
Subsignal("io3", Pins("J11", dir="i")),
),
Resource(
"rmii",
0,
Subsignal("txd0", Pins("J3", dir="o")),
Subsignal("txd1", Pins("L1", dir="o")),
Subsignal("txen", Pins("L2", dir="o")),
Subsignal("rxd0", Pins("K5", dir="i")),
Subsignal("rxd1", Pins("J5", dir="i")),
Subsignal("crs_dv", Pins("L4", dir="i")),
Subsignal("ref_clk", Pins("K4", dir="i")),
),
Resource(
"mdio",
0,
Subsignal("mdc", Pins("K3", dir="o")),
Subsignal("mdio", Pins("L3", dir="io")),
),
Resource(
"phy",
0,
Subsignal("rst", Pins("K2", dir="o")),
Subsignal("led", Pins("J2", dir="o")),
),
Resource(
"daqnet",
0,
Subsignal("led1", Pins("C4", dir="o")),
Subsignal("led2", Pins("D3", dir="o")),
Subsignal("txp", Pins("B1", dir="o")),
Subsignal("txn", Pins("B2", dir="o")),
Subsignal("rx", Pins("C1", dir="i")),
),
Resource(
"daqnet",
1,
Subsignal("led1", Pins("D2", dir="o")),
Subsignal("led2", Pins("C3", dir="o")),
Subsignal("txp", Pins("E1", dir="o")),
Subsignal("txn", Pins("D1", dir="o")),
Subsignal("rx", Pins("E3", dir="i")),
),
Resource(
"daqnet",
2,
Subsignal("led1", Pins("G3", dir="o")),
Subsignal("led2", Pins("F3", dir="o")),
Subsignal("txp", Pins("F1", dir="o")),
Subsignal("txn", Pins("F2", dir="o")),
Subsignal("rx", Pins("G2", dir="i")),
),
Resource(
"daqnet",
3,
Subsignal("led1", Pins("F4", dir="o")),
Subsignal("led2", Pins("H3", dir="o")),
Subsignal("txp", Pins("H1", dir="o")),
Subsignal("txn", Pins("H2", dir="o")),
Subsignal("rx", Pins("K1", dir="i")),
),
]
connectors = []
class AmaltheaPlatformRev0D1(LatticeECP5Platform):
""" Board description for the pre-release r0.1 revision of LUNA. """
name = "Amalthea r0.1 (26MHz mod)"
device = "LFE5U-12F"
package = "BG256"
speed = os.getenv("LUNA_SPEED_GRADE", "8")
default_clk = "clk_26MHz"
# Provide the type that'll be used to create our clock domains.
clock_domain_generator = DomainGenerator
#
# Default clock frequencies for each of our clock domains.
#
# Different revisions have different FPGA speed grades, and thus the
# default frequencies will vary.
#
DEFAULT_CLOCK_FREQUENCIES_MHZ = {
"fast": 240,
"sync": 120,
"usb": 60
}
#
# Preferred DRAM bus I/O (de)-skewing constants.
#
ram_timings = dict(
clock_skew = 64
)
# Provides any platform-specific ULPI registers necessary.
# This is the spot to put any platform-specific vendor registers that need
# to be written.
ulpi_extra_registers = {
0x39: 0b000110 # USB3343: swap D+ and D- to match the LUNA boards
}
#
# I/O resources.
#
resources = [
# 26MHz clock from AT86RF215 CLKOUT.
Resource("clk_26MHz", 0, Pins("A7", dir="i"),
Clock(26e6), Attrs(IO_TYPE="LVCMOS33")),
# Connection to our SPI flash; can be used to work with the flash
# from e.g. a bootloader.
Resource("spi_flash", 0,
# SCK is on pin 9; but doesn't have a traditional I/O buffer.
# Instead, we'll need to drive a clock into a USRMCLK instance.
# See interfaces/flash.py for more information.
Subsignal("sdi", Pins("T8", dir="o")),
Subsignal("sdo", Pins("T7", dir="i")),
# In r0.1, the chip select line can either be driven by the FPGA
# or by the Debug Controller. Accordingly, we'll mark the line as
# bidirectional, and let the user decide.
Subsignal("cs", PinsN("N8", dir="io")),
Attrs(IO_TYPE="LVCMOS33")
),
# UART connected to the debug controller; can be routed to a host via CDC-ACM.
Resource("uart", 0,
Subsignal("rx", Pins("R14", dir="i")),
Subsignal("tx", Pins("T14", dir="o")),
Attrs(IO_TYPE="LVCMOS33")
),
# SPI bus connected to the debug controller, for simple register exchanges.
# Note that the Debug Controller is the master on this bus.
Resource("debug_spi", 0,
Subsignal("sck", Pins( "R13", dir="i")),
Subsignal("sdi", Pins( "P13", dir="i")),
Subsignal("sdo", Pins( "P11", dir="o")),
Subsignal("cs", PinsN("T13", dir="i")),
Attrs(IO_TYPE="LVCMOS33")
),
# FPGA-connected LEDs.
Resource("led", 5, PinsN("P15", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 4, PinsN("N16", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 3, PinsN("M15", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 2, PinsN("M16", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 1, PinsN("L15", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 0, PinsN("L16", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
# USB PHYs
ULPIResource("sideband_phy",
data_sites="R2 R1 P2 P1 N1 M2 M1 L2", clk_site="R4",
dir_site="T3", nxt_site="T2", stp_site="T4", reset_site="R3"),
ULPIResource("host_phy",
data_sites="G2 G1 F2 F1 E1 D1 C1 C2", clk_site="K2",
dir_site="J1", nxt_site="H2", stp_site="J2", reset_site="K1"),
# HyperRAM (1V8 domain).
Resource("ram", 0,
# Note: our clock uses the pseudo-differential I/O present on the top tiles.
# This requires a recent version of trellis+nextpnr. If your build complains
# that LVCMOS18D is an invalid I/O type, you'll need to upgrade.
Subsignal("clk", DiffPairs("B14", "A15", dir="o"), Attrs(IO_TYPE="LVCMOS18D")),
Subsignal("dq", Pins("A11 B10 B12 A12 B11 A10 B9 A9", dir="io")),
Subsignal("rwds", Pins( "A13", dir="io")),
Subsignal("cs", PinsN("A14", dir="o")),
Subsignal("reset", PinsN("B13", dir="o")),
Attrs(IO_TYPE="LVCMOS18", SLEWRATE="FAST")
),
# Radio.
Resource("radio", 0,
Subsignal("rst", PinsN("C14", dir="o")),
Subsignal("sclk", Pins( "K14", dir="o")),
Subsignal("sel", PinsN("E16", dir="o")),
Subsignal("mosi", Pins( "F16", dir="o")),
Subsignal("miso", Pins( "G16", dir="i")),
Subsignal("irq", Pins( "F15", dir="i")),
Subsignal("rxclk", DiffPairs("J16", "J15", dir="i"), Attrs(IO_TYPE="LVDS", DIFFRESISTOR="100", PULLMODE="UP")),
Subsignal("rxd09", DiffPairs("D16", "E15", dir="i"), Attrs(IO_TYPE="LVDS", DIFFRESISTOR="100")),
Subsignal("rxd24", DiffPairs("K16", "K15", dir="i"), Attrs(IO_TYPE="LVDS", DIFFRESISTOR="100")),
Subsignal("txclk", DiffPairs("B16", "B15", dir="o"), Attrs(IO_TYPE="LVCMOS33D", DRIVE="4")),
Subsignal("txd", DiffPairs("C16", "C15", dir="o"), Attrs(IO_TYPE="LVCMOS33D", DRIVE="4")),
Attrs(IO_TYPE="LVCMOS33"),
),
# User I/O connections.
# TODO: Update these for io0+/- & io1+/-
Resource("user_io", 0, Pins("A5", dir="io"), Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST")),
Resource("user_io", 1, Pins("A4", dir="io"), Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST")),
Resource("user_io", 2, Pins("A3", dir="io"), Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST")),
Resource("user_io", 3, Pins("A2", dir="io"), Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST")),
]
connectors = [
# User I/O connector.
Connector("user_io", 0, """
A5 - A2
A4 - A3
""")
]
def toolchain_prepare(self, fragment, name, **kwargs):
overrides = {
'ecppack_opts': '--compress --freq 38.8'
}
return super().toolchain_prepare(fragment, name, **overrides, **kwargs)
def toolchain_program(self, products, name):
""" Programs the relevant LUNA board via its sideband connection. """
from luna.apollo import ApolloDebugger
from luna.apollo.ecp5 import ECP5_JTAGProgrammer
# Create our connection to the debug module.
debugger = ApolloDebugger()
# Grab our generated bitstream, and upload it to the FPGA.
bitstream = products.get("{}.bit".format(name))
with debugger.jtag as jtag:
programmer = ECP5_JTAGProgrammer(jtag)
programmer.configure(bitstream)
def toolchain_flash(self, products, name="top"):
""" Programs the LUNA board's flash via its sideband connection. """
from luna.apollo import ApolloDebugger
from luna.apollo.flash import ensure_flash_gateware_loaded
# Create our connection to the debug module.
debugger = ApolloDebugger()
ensure_flash_gateware_loaded(debugger, platform=self.__class__())
# Grab our generated bitstream, and upload it to the .
bitstream = products.get("{}.bit".format(name))
with debugger.flash as flash:
flash.program(bitstream)
debugger.soft_reset()
def toolchain_erase(self):
""" Erases the LUNA board's flash. """
from luna.apollo import ApolloDebugger
from luna.apollo.flash import ensure_flash_gateware_loaded
# Create our connection to the debug module.
debugger = ApolloDebugger()
ensure_flash_gateware_loaded(debugger, platform=self.__class__())
with debugger.flash as flash:
flash.erase()
debugger.soft_reset()
def connect_mainboard(self):
add_plugin_connector(
platform=self,
number="south",
conn=("JX2", 0),
lvds=["94 96", "93 95", "97 99", "87 89", "81 83", "73 75"],
)
add_plugin_connector(
platform=self,
number="north",
conn=("JX1", 0),
lvds=["68 70", "74 76", "82 84", "92 94", "93 91", "89 87"])
lvds_lanes = []
for lane, pins in CMV_LVDS_LANES.items():
lvds_lanes.append(
Subsignal(
f"lvds_{lane}",
DiffPairs(*pins, dir='i', invert=(
lane == 37)), # lane 37 inverted to simplify routing
Attrs(IOSTANDARD="LVDS_25",
DIFF_TERM="TRUE",
IBUF_LOW_PWR="TRUE")))
self.add_resources([
Resource(
"sensor",
0,
Subsignal("clk", Pins("19", dir='o', conn=("JX1", 0)),
Attrs(IOSTANDARD="LVCMOS25")),
Subsignal("reset", PinsN("17", dir='o', conn=("JX1", 0)),
Attrs(IOSTANDARD="LVCMOS25")),
Subsignal("frame_req", Pins("9", dir='o', conn=("JX1", 0)),
Attrs(IOSTANDARD="LVCMOS25")),
Subsignal("t_exp1", Pins("10", dir='o', conn=("JX1", 0)),
Attrs(IOSTANDARD="LVCMOS25")),
Subsignal("t_exp2", Pins("100", dir='o', conn=("JX2", 0)),
Attrs(IOSTANDARD="LVCMOS25")),
Subsignal("lvds_clk",
DiffPairs("81", "83", dir='o', conn=("JX1", 0)),
Attrs(IOSTANDARD="LVDS_25")),
*lvds_lanes,
Subsignal(
"lvds_ctrl", DiffPairs("82",
"84",
dir='i',
conn=("JX2", 0)),
Attrs(IOSTANDARD="LVDS_25",
DIFF_TERM="TRUE",
IBUF_LOW_PWR="TRUE")),
Subsignal(
"lvds_outclk",
DiffPairsN("48", "50", dir='i', conn=("JX1", 0)),
Attrs(IOSTANDARD="LVDS_25",
DIFF_TERM="TRUE",
IBUF_LOW_PWR="TRUE")),
),
Resource(
"sensor_spi",
0,
Subsignal("cs", Pins("24", dir='o', conn=("JX1", 0)),
Attrs(IOSTANDARD="LVCMOS25")),
Subsignal("clk", Pins("26", dir='o', conn=("JX1", 0)),
Attrs(IOSTANDARD="LVCMOS25")),
Subsignal("copi", Pins("29", dir='o', conn=("JX2", 0)),
Attrs(IOSTANDARD="LVCMOS25")),
Subsignal("cipo", Pins("31", dir='i', conn=("JX2", 0)),
Attrs(IOSTANDARD="LVCMOS25")),
),
])
# TODO: add ext & shield connectors (but how?)
# best would be a way to (transpranetly) handle the routing fabrics
self.add_resources([
Resource("routing", 'east',
DiffPairs('29', '31', dir='io', conn=("JX2", 0)),
Attrs(IOSTANDARD="LVCMOS33")),
Resource("routing", 'west', Pins("56", dir='o', conn=("JX1", 0)),
Attrs(IOSTANDARD="LVCMOS33")),
])
def elaborate(self, platform: ZynqSocPlatform):
platform.add_resources([
Resource(
"loopback",
0,
# high speed serial lanes
Subsignal("tx",
DiffPairs("1", "7", dir='o', conn=("pmod", "south")),
Attrs(IOSTANDARD="LVDS_25")),
Subsignal("rx",
DiffPairs("8", "2", dir='i', conn=("pmod", "south")),
Attrs(IOSTANDARD="LVDS_25")),
)
])
m = Module()
# clock_setup: the serdes clockdomain has double the frequency of fclk1
platform.ps7.fck_domain()
pll = m.submodules.pll = _Pll(startup_wait=False,
ref_jitter1=0.01,
clkin1_period=8.0,
clkfbout_mult=8,
divclk_divide=1,
clkout0_divide=16,
clkout0_phase=0.0,
clkout1_divide=4,
clkout1_phase=0.0)
platform.ps7.fck_domain(requested_frequency=200e6,
domain_name="pll_clk_in")
m.d.comb += pll.clk.in_[1].eq(ClockSignal("pll_clk_in"))
m.d.comb += pll.clk.fbin.eq(pll.clk.fbout)
bufg_serdes = m.submodules.bufg_serdes = BufG(pll.clk.out[0])
m.domains += ClockDomain("serdes")
m.d.comb += ClockSignal("serdes").eq(bufg_serdes.o)
bufg_serdes_4x = m.submodules.bufg_serdes_4x = BufG(pll.clk.out[1])
m.domains += ClockDomain("serdes_4x")
m.d.comb += ClockSignal("serdes_4x").eq(bufg_serdes_4x.o)
# make the design resettable via a axi register
reset_serdes = ControlSignal()
for domain in ["sync", "serdes", "serdes_4x"]:
m.d.comb += ResetSignal(domain).eq(reset_serdes)
# loopback
loopback = platform.request("loopback")
## sender side
to_oserdes = Signal(8)
oserdes = m.submodules.oserdes = _OSerdes(data_width=8,
tristate_width=1,
data_rate_oq="ddr",
serdes_mode="master",
data_rate_tq="buf")
m.d.comb += oserdes.oce.eq(1)
m.d.comb += oserdes.clk.eq(ClockSignal("serdes_4x"))
m.d.comb += oserdes.clkdiv.eq(ClockSignal("serdes"))
m.d.comb += oserdes.rst.eq(ResetSignal("serdes"))
m.d.comb += Cat(oserdes.d[i] for i in reversed(range(1, 9))).eq(
to_oserdes) # reversed is needed!!1
m.d.comb += loopback.tx.eq(oserdes.oq)
## reciver side
bufg_idelay_refclk = m.submodules.bufg_idelay_refclk = BufG(
pll.clk.out[1])
m.domains += ClockDomain("idelay_refclk")
m.d.comb += ClockSignal("idelay_refclk").eq(bufg_idelay_refclk.o)
idelay_ctl = m.submodules.idelay_ctl = _IDelayCtrl()
m.d.comb += StatusSignal(name="idelay_crl_rdy").eq(idelay_ctl.rdy)
m.d.comb += idelay_ctl.refclk.eq(ClockSignal("idelay_refclk"))
m.d.comb += idelay_ctl.rst.eq(ResetSignal("idelay_refclk"))
idelay = m.submodules.idelay = _IDelay(delay_src="iDataIn",
signal_pattern="data",
cinvctrl_sel=False,
high_performance_mode=True,
refclk_frequency=200.0,
pipe_sel=False,
idelay_type="var_load",
idelay_value=0)
m.d.comb += idelay.c.eq(
ClockSignal()
) # this is really the clock to which the control inputs are syncronous!
m.d.comb += idelay.ld.eq(ControlSignal(name="idelay_ld"))
m.d.comb += idelay.ldpipeen.eq(0)
m.d.comb += idelay.ce.eq(0)
m.d.comb += idelay.inc.eq(0)
m.d.comb += idelay.cntvalue.in_.eq(
ControlSignal(5, name="idelay_cntvaluein"))
m.d.comb += StatusSignal(5, name="idelay_cntvalueout").eq(
idelay.cntvalue.out)
m.d.comb += idelay.idatain.eq(loopback.rx)
idelay_out = Signal()
m.d.comb += idelay_out.eq(idelay.data.out)
iserdes = m.submodules.iserdes = _ISerdes(
data_width=8,
data_rate="ddr",
serdes_mode="master",
interface_type="networking",
num_ce=1,
iobDelay="ifd",
)
m.d.comb += iserdes.ddly.eq(idelay_out)
m.d.comb += iserdes.ce[1].eq(1)
m.d.comb += iserdes.clk.eq(ClockSignal("serdes_4x"))
m.d.comb += iserdes.clkb.eq(~ClockSignal("serdes_4x"))
m.d.comb += iserdes.rst.eq(ResetSignal("serdes"))
m.d.comb += iserdes.clkdiv.eq(ClockSignal("serdes"))
from_iserdes = Signal(8)
m.d.comb += from_iserdes.eq(Cat(iserdes.q[i] for i in range(1, 9)))
## check logic
last_received = StatusSignal(8, name="last_received")
current_state = StatusSignal(32, name="current_state")
training_cycles = StatusSignal(32, name="training_cycles")
slipped_bits = StatusSignal(32, name="slipped_bits")
error_cnt = StatusSignal(32, name="error_cnt")
success_cnt = StatusSignal(32, name="success_cnt")
last_current_out = StatusSignal(24, name="last_current_out")
test_pattern = ControlSignal(8, name="test_patern")
with m.FSM(domain="serdes"):
with m.State("TRAINING"):
m.d.comb += current_state.eq(0)
# start the link with correcting for the bitslip
training_pattern = 0b00001111
m.d.serdes += to_oserdes.eq(training_pattern)
since_bitslip = Signal(2)
m.d.serdes += training_cycles.eq(training_cycles + 1)
with m.If(iserdes.bitslip == 1):
m.d.serdes += iserdes.bitslip.eq(0)
m.d.serdes += since_bitslip.eq(0)
with m.Elif(since_bitslip < 3):
m.d.serdes += since_bitslip.eq(since_bitslip + 1)
with m.Elif(from_iserdes != training_pattern):
m.d.serdes += iserdes.bitslip.eq(1)
m.d.serdes += slipped_bits.eq(slipped_bits + 1)
with m.Else():
m.d.serdes += to_oserdes.eq(0x00)
m.next = "RUNNING"
with m.State("RUNNING"):
m.d.comb += current_state.eq(1)
with m.If(test_pattern):
m.d.serdes += to_oserdes.eq(test_pattern)
with m.If(from_iserdes == test_pattern):
m.d.serdes += success_cnt.eq(success_cnt + 1)
with m.Else():
m.d.serdes += error_cnt.eq(error_cnt + 1)
with m.Else():
m.d.serdes += to_oserdes.eq(to_oserdes + 1)
with m.If(from_iserdes == (last_received + 1)[0:8]):
m.d.serdes += success_cnt.eq(success_cnt + 1)
with m.Else():
m.d.serdes += error_cnt.eq(error_cnt + 1)
m.d.serdes += last_received.eq(from_iserdes)
m.d.comb += last_current_out.eq(
Cat(last_received, from_iserdes, to_oserdes))
return m
class OrangeCrabR0D1(OrangeCrabPlatform, LUNAPlatform):
""" Board description for OrangeCrab r0.1. """
name = "OrangeCrab r0.1"
#
# I/O resources.
#
resources = [
Resource("clk_48MHz", 0, Pins("A9"), Attrs(IO_TYPE="LVCMOS33"),
Clock(48e6)),
Resource(
"rgb_led",
0,
Subsignal("r", Pins("V17"), Attrs(IO_TYPE="LVCMOS33")),
Subsignal("g", Pins("T17"), Attrs(IO_TYPE="LVCMOS33")),
Subsignal("b", Pins("J3"), Attrs(IO_TYPE="LVCMOS33")),
),
Resource(
"ddram", 0,
Subsignal("a", Pins("A4 D2 C3 C7 D3 D4 D1 B2 C1 A2 A7 C2 C4"),
Attrs(IO_TYPE="SSTL135_I")),
Subsignal("ba", Pins("B6 B7 A6"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("ras_n", Pins("C12"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("cas_n", Pins("D13"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("we_n", Pins("B12"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("cs_n", Pins("A12"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("dm", Pins("D16 G16"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal(
"dq",
Pins(
"C17 D15 B17 C16 A15 B13 A17 A13 F17 F16 G15 F15 J16 C18 H16 F18"
), Attrs(IO_TYPE="SSTL135_I", TERMINATION="75")),
Subsignal(
"dqs_p", Pins("B15 G18"),
Attrs(IO_TYPE="SSTL135D_I",
TERMINATION="OFF",
DIFFRESISTOR="100")),
Subsignal("clk_p", Pins("J18"), Attrs(IO_TYPE="SSTL135D_I")),
Subsignal("cke", Pins("D6"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("odt", Pins("C13"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("reset_n", Pins("B1"), Attrs(IO_TYPE="SSTL135_I")),
Attrs(SLEWRATE="FAST")),
Resource("spiflash4x", 0, Subsignal("cs_n", Pins("U17")),
Subsignal("clk", Pins("U16")),
Subsignal("dq", Pins("U18 T18 R18 N18")),
Attrs(IO_TYPE="LVCMOS33")),
Resource("spi-internal", 0,
Subsignal("cs_n", Pins("B11"), Attrs(PULLMODE="UP")),
Subsignal("clk", Pins("C11")),
Subsignal("miso", Pins("A11"), Attrs(PULLMODE="UP")),
Subsignal("mosi", Pins("A10"), Attrs(PULLMODE="UP")),
Attrs(IO_TYPE="LVCMOS33", SLEWRATE="SLOW")),
Resource(
"spisdcard",
0,
Subsignal("clk", Pins("K1")),
Subsignal("mosi", Pins("K2"), Attrs(PULLMODE="UP")),
Subsignal("cs_n", Pins("M1"), Attrs(PULLMODE="UP")),
Subsignal("miso", Pins("J1"), Attrs(PULLMODE="UP")),
Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST"),
),
# USB Connector.
Resource("usb", 0, Subsignal("d_p", Pins("N1", dir="io")),
Subsignal("d_n", Pins("M2", dir="io")),
Subsignal("pullup", Pins("N2", dir="o")),
Attrs(IO_TYPE="LVCMOS33")),
]
connectors = [
Connector(
"GPIO", 0,
"N17 M18 C10 C9 - B10 B9 - - C8 B8 A8 H2 J2 N15 R17 N16 - - - - - - - -"
)
]
def elaborate(self, platform):
m = Module()
# Generate our domain clocks/resets.
m.submodules.car = self.car
# acm = USBSerialDeviceExample()
# m.submodules.acm = acm
ts = DomainRenamer({"sync": "usb"})(self.spork)
m.submodules.ts = ts
return m
if __name__ == "__main__":
pl = TinyFPGABxPlatform()
pl.add_resources([
UARTResource(0,
rx="A8",
tx="B8",
attrs=Attrs(IO_STANDARD="SB_LVCMOS", PULLUP=1)),
Resource("reset_pin", 0, Pins("18", conn=("gpio", 0), dir="i")),
# *ButtonResources(pins="10", invert=True, attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
*LEDResources("blinky",
pins="J1 H2 H9 D9",
attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
])
construct = UPPER(pl, HexLoader)
pl.build(construct, do_program=True)
class DaishoPlatform(IntelPlatform):
""" Board description for Daisho boards."""
name = "Daisho"
device = "EEP4CE30F29C8"
default_clk = "clk_60MHz"
#
# Default clock frequencies for each of our clock domains.
#
# Different revisions have different FPGA speed grades, and thus the
# default frequencies will vary.
#
DEFAULT_CLOCK_FREQUENCIES_MHZ = {
"fast": 120,
"sync": 60,
"ulpi": 60
}
#
# Preferred DRAM bus I/O (de)-skewing constants.
#
ram_timings = dict(
clock_skew = 64
)
# Provides any platform-specific ULPI registers necessary.
# This is the spot to put any platform-specific vendor registers that need
# to be written.
ulpi_extra_registers = {
0x39: 0b000110 # USB3343: swap D+ and D- to match the LUNA boards
}
#
# I/O resources.
#
resources = [
# Primary, discrete 60MHz oscillator.
Resource("clk_60MHz", 0, Pins("A8", dir="i"),
Clock(60e6), Attrs(IO_TYPE="LVCMOS33")),
# Connection to our SPI flash; can be used to work with the flash
# from e.g. a bootloader.
Resource("spi_flash", 0,
# SCK is on pin 9; but doesn't have a traditional I/O buffer.
# Instead, we'll need to drive a clock into a USRMCLK instance.
# See interfaces/flash.py for more information.
Subsignal("sdi", Pins("T8", dir="o")),
Subsignal("sdo", Pins("T7", dir="i")),
# In r0.1, the chip select line can either be driven by the FPGA
# or by the Debug Controller. Accordingly, we'll mark the line as
# bidirectional, and let the user decide.
Subsignal("cs", PinsN("N8", dir="io")),
Attrs(IO_TYPE="LVCMOS33")
),
#
# Note: r0.1 has a DFM issue that makes it difficult to solder a BGA with
# reliable connections on the intended SCK pin (P12), and lacks a CS pin on the
# debug SPI; which seems like a silly omission.
#
# Accordingly, we're mapping the debug SPI and UART over the same pins, as the
# microcontroller can use either.
#
# UART connected to the debug controller; can be routed to a host via CDC-ACM.
Resource("uart", 0,
Subsignal("rx", Pins("R14", dir="i")),
Subsignal("tx", Pins("T14", dir="o")),
Attrs(IO_TYPE="LVCMOS33")
),
# SPI bus connected to the debug controller, for simple register exchanges.
# Note that the Debug Controller is the master on this bus.
Resource("debug_spi", 0,
Subsignal("sck", Pins( "R14", dir="i")),
Subsignal("sdi", Pins( "P13", dir="i")),
Subsignal("sdo", Pins( "P11", dir="o")),
Subsignal("cs", PinsN("T14", dir="i")),
Attrs(IO_TYPE="LVCMOS33")
),
# FPGA-connected LEDs.
Resource("led", 5, PinsN("P15", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 4, PinsN("N16", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 3, PinsN("M15", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 2, PinsN("M16", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 1, PinsN("L15", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 0, PinsN("L16", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
# USB PHYs
ULPIResource("sideband_phy",
data_sites="R2 R1 P2 P1 N1 M2 M1 L2", clk_site="R4",
dir_site="T3", nxt_site="T2", stp_site="T4", reset_site="R3"),
ULPIResource("host_phy",
data_sites="G2 G1 F2 F1 E1 D1 C1 B1", clk_site="K2",
dir_site="J1", nxt_site="H2", stp_site="J2", reset_site="K1"),
ULPIResource("target_phy",
data_sites="D16 E15 E16 F15 F16 G15 J16 K16", clk_site="B15",
dir_site="C15", nxt_site="C16", stp_site="B16", reset_site="G16"),
# Target port power switching
# Note: the r0.1 boards that have been produced incorrectly use the AP22814B
# instead of the AP22814A. This inverts the load-switch enables.
#
Resource("power_a_port", 0, PinsN("C14", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("pass_through_vbus", 0, PinsN("D14", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("target_vbus_fault", 0, Pins("K15", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
# HyperRAM (1V8 domain).
Resource("ram", 0,
# Note: our clock uses the pseudo-differential I/O present on the top tiles.
# This requires a recent version of trellis+nextpnr. If your build complains
# that LVCMOS18D is an invalid I/O type, you'll need to upgrade.
Subsignal("clk", DiffPairs("B14", "A15", dir="o"), Attrs(IO_TYPE="LVCMOS18D")),
Subsignal("dq", Pins("A11 B10 B12 A12 B11 A10 B9 A9", dir="io")),
Subsignal("rwds", Pins( "A13", dir="io")),
Subsignal("cs", PinsN("A14", dir="o")),
Subsignal("reset", PinsN("B13", dir="o")),
Attrs(IO_TYPE="LVCMOS18", SLEWRATE="FAST")
),
# User I/O connections.
Resource("user_io", 0, Pins("A5", dir="io"), Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST")),
Resource("user_io", 1, Pins("A4", dir="io"), Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST")),
Resource("user_io", 2, Pins("A3", dir="io"), Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST")),
Resource("user_io", 3, Pins("A2", dir="io"), Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST")),
]
connectors = [
# User I/O connector.
Connector("user_io", 0, """
A5 - A2
A4 - A3
""")
]
def toolchain_prepare(self, fragment, name, **kwargs):
overrides = {
'ecppack_opts': '--compress --idcode {} --freq 38.8'.format(0x21111043)
}
return super().toolchain_prepare(fragment, name, **overrides, **kwargs)
def toolchain_program(self, products, name):
""" Programs the relevant LUNA board via its sideband connection. """
from luna.apollo import ApolloDebugger
from luna.apollo.ecp5 import ECP5_JTAGProgrammer
# Create our connection to the debug module.
debugger = ApolloDebugger()
# Grab our generated bitstream, and upload it to the FPGA.
bitstream = products.get("{}.bit".format(name))
with debugger.jtag as jtag:
programmer = ECP5_JTAGProgrammer(jtag)
programmer.configure(bitstream)
def toolchain_flash(self, products, name="top"):
""" Programs the LUNA board's flash via its sideband connection. """
from luna.apollo import ApolloDebugger
from luna.apollo.flash import ensure_flash_gateware_loaded
# Create our connection to the debug module.
debugger = ApolloDebugger()
ensure_flash_gateware_loaded(debugger, platform=self.__class__())
# Grab our generated bitstream, and upload it to the .
bitstream = products.get("{}.bit".format(name))
with debugger.flash as flash:
flash.program(bitstream)
debugger.soft_reset()
def toolchain_erase(self):
""" Erases the LUNA board's flash. """
from luna.apollo import ApolloDebugger
from luna.apollo.flash import ensure_flash_gateware_loaded
# Create our connection to the debug module.
debugger = ApolloDebugger()
ensure_flash_gateware_loaded(debugger, platform=self.__class__())
with debugger.flash as flash:
flash.erase()
debugger.soft_reset()
class ColorLite5A75E_V6_0_Platform(LatticeECP5Platform):
device = "LFE5U-25F"
package = "BG256"
speed = "6"
default_clk = "clk25"
lvcmos = Attrs(IO_TYPE="LVCMOS33")
resources = [
Resource("clk25", 0, Pins("P6", dir="i"), Clock(25e6), lvcmos),
Resource("led", 0, Pins("T6", dir="o"), lvcmos),
Resource("key", 0, PinsN("R7", dir="i"), lvcmos),
Resource("flash", 0, Subsignal("cs", Pins("N8", dir="o"), lvcmos),
Subsignal("so", Pins("T7", dir="i"), lvcmos),
Subsignal("si", Pins("T8", dir="o"), lvcmos)),
Resource("led_common", 0, Subsignal("a", Pins("N5", dir="o"), lvcmos),
Subsignal("b", Pins("N3", dir="o"), lvcmos),
Subsignal("c", Pins("P3", dir="o"), lvcmos),
Subsignal("d", Pins("P4", dir="o"), lvcmos),
Subsignal("e", Pins("N4", dir="o"), lvcmos),
Subsignal("clk", Pins("M3", dir="o"), lvcmos),
Subsignal("lat", Pins("N1", dir="o"), lvcmos),
Subsignal("oe", Pins("M4", dir="o"), lvcmos)),
Resource("eth_common", 0, Subsignal("mdc", Pins("R5", dir="o"),
lvcmos),
Subsignal("mdio", Pins("T4", dir="io"), lvcmos),
Subsignal("rst", PinsN("R6", dir="o"), lvcmos)),
Resource("phy", 0, Subsignal("txc", Pins("L1", dir="o"), lvcmos),
Subsignal("txd", Pins("M2 M1 P1 R1", dir="o"), lvcmos),
Subsignal("txctl", Pins("L2", dir="o"), lvcmos),
Subsignal("rxc", Pins("J1", dir="i"), lvcmos),
Subsignal("rxd", Pins("J3 K2 K1 K3", dir="i"), lvcmos),
Subsignal("rxctl", Pins("J2", dir="i"), lvcmos)),
Resource("phy", 1, Subsignal("txc", Pins("J16", dir="o"), lvcmos),
Subsignal("txd", Pins("K16 J15 J14 K15", dir="o"), lvcmos),
Subsignal("txctl", Pins("K14", dir="o"), lvcmos),
Subsignal("rxc", Pins("M16", dir="i"), lvcmos),
Subsignal("rxd", Pins("M15 R16 L15 L16", dir="i"), lvcmos),
Subsignal("rxctl", Pins("P16", dir="i"), lvcmos)),
Resource(
"sdram", 0, Subsignal("we", PinsN("B5", dir="o"), lvcmos),
Subsignal("cas", PinsN("A6", dir="o"), lvcmos),
Subsignal("ras", PinsN("B6", dir="o"), lvcmos),
Subsignal("ba", Pins("B7 A8", dir="o"), lvcmos),
Subsignal("a", Pins("A9 B9 B10 C10 D9 C9 E9 D8 E8 C7 B8", dir="o"),
lvcmos),
Subsignal(
"d",
Pins(
"D5 C5 E5 C6 D6 E6 D7 E7 D10 C11 D11 C12 E10 C13 "
"D13 E11 A5 B4 A4 B3 A3 C3 A2 B2 D14 B14 A14 B13 "
"A13 B12 B11 A11",
dir="io"), lvcmos),
Subsignal("clk", Pins("C8", dir="o"), lvcmos)),
]
connectors = []
# Used by __init__ to create each individual LED pin header
leds = [
# R0, G0, B0, R1, G1, B1
['C4', 'D4', 'E4', 'D3', 'E3', 'F4'], # J1
['F3', 'F5', 'G3', 'G4', 'H3', 'H4'], # J2
['G5', 'H5', 'J5', 'J4', 'B1', 'C2'], # J3
['C1', 'D1', 'E2', 'E1', 'F2', 'F1'], # J4
['G2', 'G1', 'H2', 'K5', 'K4', 'L3'], # J5
['L4', 'L5', 'P2', 'R2', 'T2', 'R3'], # J6
['T3', 'R4', 'M5', 'P5', 'N6', 'N7'], # J7
['P7', 'M7', 'P8', 'R8', 'M8', 'M9'], # J8
['P11', 'N11', 'M11', 'T13', 'R12', 'R13'], # J9
['R14', 'T14', 'D16', 'C15', 'C16', 'B16'], # J10
['B15', 'C14', 'T15', 'P15', 'R15', 'P12'], # J11
['P13', 'N12', 'N13', 'M12', 'P14', 'N14'], # J12
['H15', 'H14', 'G16', 'F16', 'G15', 'F15'], # J13
['E15', 'E16', 'L12', 'L13', 'M14', 'L14'], # J14
['J13', 'K13', 'J12', 'H13', 'H12', 'G12'], # J15
['G14', 'G13', 'F12', 'F13', 'F14', 'E14'], # J16
]
# Currently unknown inputs/outputs/bidirectional
inputs = ['A10', 'A12']
outputs = ['A7', 'A15', 'E12', 'E13', 'K12', 'M6', 'M13']
bidis = ['D12']
def __init__(self):
lvcmos = self.lvcmos
# Create resources for each LED header
for jidx, pins in enumerate(self.leds):
self.resources += [
Resource("led_rgb", jidx,
Subsignal("r0", Pins(pins[0], dir="o"), lvcmos),
Subsignal("g0", Pins(pins[1], dir="o"), lvcmos),
Subsignal("b0", Pins(pins[2], dir="o"), lvcmos),
Subsignal("r1", Pins(pins[3], dir="o"), lvcmos),
Subsignal("g1", Pins(pins[4], dir="o"), lvcmos),
Subsignal("b1", Pins(pins[5], dir="o"), lvcmos))
]
# Create resources for each unknown pin
for pin in self.outputs:
self.resources += [Resource(pin, 0, Pins(pin, dir="o"), lvcmos)]
for pin in self.inputs:
self.resources += [Resource(pin, 0, Pins(pin, dir="i"), lvcmos)]
for pin in self.bidis:
self.resources += [Resource(pin, 0, Pins(pin, dir="io"), lvcmos)]
super().__init__()
class ECPIX5PlatformRev02(LatticeECP5Platform, LUNAPlatform):
name = "ECPIX-5 R02"
device = "LFE5UM5G-85F"
package = "BG554"
speed = "8"
default_clk = "clk100"
default_rst = "rst"
# Provide the type that'll be used to create our clock domains.
clock_domain_generator = StubClockDomainGenerator
# We only have a single PHY; so use it directly.
default_usb_connection = "ulpi"
resources = [
Resource("rst", 0, PinsN("AB1", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
Resource("clk100", 0, Pins("K23", dir="i"), Clock(100e6),
Attrs(IO_TYPE="LVCMOS33")),
# LEDs
Resource(
"rgb_led",
0,
Subsignal("r", Pins("U21")),
Subsignal("g", Pins("W21")),
Subsignal("b", Pins("T24")),
Attrs(IO_TYPE="LVCMOS33"),
),
Resource(
"rgb_led",
1,
Subsignal("r", Pins("T23")),
Subsignal("g", Pins("R21")),
Subsignal("b", Pins("T22")),
Attrs(IO_TYPE="LVCMOS33"),
),
Resource(
"rgb_led",
2,
Subsignal("r", Pins("P21")),
Subsignal("g", Pins("R23")),
Subsignal("b", Pins("P22")),
Attrs(IO_TYPE="LVCMOS33"),
),
Resource(
"rgb_led",
3,
Subsignal("r", Pins("K21")),
Subsignal("g", Pins("K24")),
Subsignal("b", Pins("M21")),
Attrs(IO_TYPE="LVCMOS33"),
),
Resource("uart", 0, Subsignal("rx", Pins("R26", dir="i")),
Subsignal("tx", Pins("R24", dir="o")),
Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP")),
Resource("eth_rgmii", 0, Subsignal("rst", PinsN("C13", dir="o")),
Subsignal("mdio", Pins("A13", dir="io")),
Subsignal("mdc", Pins("C11", dir="o")),
Subsignal("tx_clk", Pins("A12", dir="o")),
Subsignal("tx_ctrl", Pins("C9", dir="o")),
Subsignal("tx_data", Pins("D8 C8 B8 A8", dir="o")),
Subsignal("rx_clk", Pins("E11", dir="i")),
Subsignal("rx_ctrl", Pins("A11", dir="i")),
Subsignal("rx_data", Pins("B11 A10 B10 A9", dir="i")),
Attrs(IO_TYPE="LVCMOS33")),
Resource("eth_int", 0, PinsN("B13", dir="i"),
Attrs(IO_TYPE="LVCMOS33")),
Resource(
"ddr3", 0,
Subsignal("clk", DiffPairs("H3", "J3", dir="o"),
Attrs(IO_TYPE="SSTL135D_I")),
Subsignal("clk_en", Pins("P1", dir="o")),
Subsignal("we", PinsN("R3", dir="o")),
Subsignal("ras", PinsN("T3", dir="o")),
Subsignal("cas", PinsN("P2", dir="o")),
Subsignal(
"a",
Pins("T5 M3 L3 V6 K2 W6 K3 L1 H2 L2 N1 J1 M1 K1", dir="o")),
Subsignal("ba", Pins("U6 N3 N4", dir="o")),
Subsignal("dqs", DiffPairs("V4 V1", "U5 U2", dir="io"),
Attrs(IO_TYPE="SSTL135D_I")),
Subsignal(
"dq",
Pins("T4 W4 R4 W5 R6 P6 P5 P4 R1 W3 T2 V3 U3 W1 T1 W2",
dir="io")), Subsignal("dm", Pins("J4 H5", dir="o")),
Subsignal("odt", Pins("L2", dir="o")), Attrs(IO_TYPE="SSTL135_I")),
Resource(
"hdmi", 0, Subsignal("rst", PinsN("N6", dir="o")),
Subsignal("scl", Pins("C17", dir="io")),
Subsignal("sda", Pins("E17", dir="io")),
Subsignal("pclk", Pins("C1", dir="o")),
Subsignal("vsync", Pins("A4", dir="o")),
Subsignal("hsync", Pins("B4", dir="o")),
Subsignal("de", Pins("A3", dir="o")),
Subsignal(
"d",
Subsignal(
"b",
Pins("AD25 AC26 AB24 AB25 B3 C3 D3 B1 C2 D2 D1 E3",
dir="o")),
Subsignal(
"g",
Pins("AA23 AA22 AA24 AA25 E1 F2 F1 D17 D16 E16 J6 H6",
dir="o")),
Subsignal(
"r",
Pins("AD26 AE25 AF25 AE26 E10 D11 D10 C10 D9 E8 H5 J4",
dir="o")),
), Subsignal("mclk", Pins("E19", dir="o")),
Subsignal("sck", Pins("D6", dir="o")),
Subsignal("ws", Pins("C6", dir="o")),
Subsignal("i2s", Pins("A6 B6 A5 C5", dir="o")),
Subsignal("int", PinsN("C4", dir="i")), Attrs(IO_TYPE="LVTTL33")),
Resource("sata", 0, Subsignal("tx", DiffPairs("AD16", "AD17",
dir="o")),
Subsignal("rx", DiffPairs("AF15", "AF16", dir="i")),
Attrs(IO_TYPE="LVDS")),
ULPIResource("ulpi",
data_sites="M26 L25 L26 K25 K26 J23 P25 H25",
clk_site="H24",
dir_site="F22",
stp_site="H23",
nxt_site="F23",
reset_site="E23",
attrs=Attrs(IO_TYPE="LVCMOS33")),
Resource("usbc_cfg", 0, Subsignal("scl", Pins("D24", dir="io")),
Subsignal("sda", Pins("C24", dir="io")),
Subsignal("dir", Pins("B23", dir="i")),
Subsignal("id", Pins("D23", dir="i")),
Subsignal("int", PinsN("B24", dir="i")),
Attrs(IO_TYPE="LVCMOS33")),
Resource(
"usbc_mux",
0,
Subsignal("en", Pins("C23", dir="oe")),
Subsignal("amsel", Pins("B26", dir="oe")),
Subsignal("pol", Pins("D26", dir="o")),
#Subsignal("lna", DiffPairs( "AF9", "AF10", dir="i"), Attrs(IO_TYPE="LVCMOS18D")),
#Subsignal("lnb", DiffPairs("AD10", "AD11", dir="o"), Attrs(IO_TYPE="LVCMOS18D")),
#Subsignal("lnc", DiffPairs( "AD7", "AD8", dir="o"), Attrs(IO_TYPE="LVCMOS18D")),
#Subsignal("lnd", DiffPairs( "AF6", "AF7", dir="i"), Attrs(IO_TYPE="LVCMOS18D")),
Attrs(IO_TYPE="LVCMOS33")),
# Compatibility aliases.
Resource("led", 0, Pins("W21", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 1, Pins("R21", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 2, Pins("R23", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 3, Pins("K24", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("user_io", 0, Pins("T25")),
Resource("user_io", 1, Pins("U25")),
Resource("user_io", 2, Pins("U24")),
Resource("user_io", 3, Pins("V24")),
]
connectors = [
Connector("pmod", 0, "T25 U25 U24 V24 - - T26 U26 V26 W26 - -"),
Connector("pmod", 1, "U23 V23 U22 V21 - - W25 W24 W23 W22 - -"),
Connector("pmod", 2, "J24 H22 E21 D18 - - K22 J21 H21 D22 - -"),
Connector("pmod", 3, " E4 F4 E6 H4 - - F3 D4 D5 F5 - -"),
Connector("pmod", 4, "E26 D25 F26 F25 - - A25 A24 C26 C25 - -"),
Connector("pmod", 5, "D19 C21 B21 C22 - - D21 A21 A22 A23 - -"),
Connector("pmod", 6, "C16 B17 C18 B19 - - A17 A18 A19 C19 - -"),
Connector("pmod", 7, "D14 B14 E14 B16 - - C14 A14 A15 A16 - -"),
]
@property
def file_templates(self):
return {
**super().file_templates, "{{name}}-openocd.cfg":
r"""
interface ftdi
ftdi_vid_pid 0x0403 0x6010
ftdi_channel 0
ftdi_layout_init 0xfff8 0xfffb
reset_config none
adapter_khz 25000
jtag newtap ecp5 tap -irlen 8 -expected-id 0x81113043
"""
}
def toolchain_program(self, products, name):
openocd = os.environ.get("OPENOCD", "openocd")
with products.extract("{}-openocd.cfg".format(name), "{}.svf".format(name)) \
as (config_filename, vector_filename):
subprocess.check_call([
openocd, "-f", config_filename, "-c",
"transport select jtag; init; svf -quiet {}; exit".format(
vector_filename)
])
class Supercon2019Badge(LatticeECP5Platform, LUNAPlatform):
""" Platform for the Supercon 2019 badge (final, black PCB). """
name = "HAD Supercon 2019 Badge"
device = "LFE5U-45F"
package = "BG381"
speed = "8"
default_clk = "clk8"
# Provide the type that'll be used to create our clock domains.
clock_domain_generator = SuperconDomainGenerator
# We only have a direct connection on our USB lines, so use that for USB comms.
default_usb_connection = "usb"
#
# I/O resources.
#
resources = [
Resource("clk8", 0, Pins("U18"), Clock(8e6),
Attrs(IOStandard="LVCMOS33")),
Resource("programn", 0, Pins("R1"), Attrs(IOStandard="LVCMOS33")),
Resource(
"serial",
0,
Subsignal("rx", Pins("U2"), Attrs(IOStandard="LVCMOS33"),
Attrs(PULLMODE="UP")),
Subsignal("tx", Pins("U1"), Attrs(IOStandard="LVCMOS33")),
),
# Full LED array.
Resource("led_anodes", 0,
Pins("E3 D3 C3 C4 C2 B1 B20 B19 A18 K20 K19"),
Attrs(IOStandard="LVCMOS33")), # Anodes
Resource("led_cathodes", 1, Pins("P19 L18 K18"),
Attrs(IOStandard="LVCMOS33")), # Cathodes via FET
# Compatibility aliases.
Resource("led", 0, Pins("E3")),
Resource("led", 1, Pins("D3")),
Resource("led", 2, Pins("C3")),
Resource("led", 3, Pins("C4")),
Resource("led", 4, Pins("C2")),
Resource("led", 5, Pins("B1")),
Resource("usb", 0, Subsignal("d_p", Pins("F3")),
Subsignal("d_n", Pins("G3")),
Subsignal("pullup", Pins("E4", dir="o")),
Subsignal("vbus_valid", Pins("F4", dir="i")),
Attrs(IOStandard="LVCMOS33")),
Resource(
"keypad",
0,
Subsignal("left", Pins("G2"), Attrs(PULLMODE="UP")),
Subsignal("right", Pins("F2"), Attrs(PULLMODE="UP")),
Subsignal("up", Pins("F1"), Attrs(PULLMODE="UP")),
Subsignal("down", Pins("C1"), Attrs(PULLMODE="UP")),
Subsignal("start", Pins("E1"), Attrs(PULLMODE="UP")),
Subsignal("select", Pins("D2"), Attrs(PULLMODE="UP")),
Subsignal("a", Pins("D1"), Attrs(PULLMODE="UP")),
Subsignal("b", Pins("E2"), Attrs(PULLMODE="UP")),
),
Resource(
"hdmi_out",
0,
Subsignal("clk_p", PinsN("P20"), Attrs(IOStandard="TMDS_33")),
Subsignal("clk_n", PinsN("R20"), Attrs(IOStandard="TMDS_33")),
Subsignal("data0_p", Pins("N19"), Attrs(IOStandard="TMDS_33")),
Subsignal("data0_n", Pins("N20"), Attrs(IOStandard="TMDS_33")),
Subsignal("data1_p", Pins("L20"), Attrs(IOStandard="TMDS_33")),
Subsignal("data1_n", Pins("M20"), Attrs(IOStandard="TMDS_33")),
Subsignal("data2_p", Pins("L16"), Attrs(IOStandard="TMDS_33")),
Subsignal("data2_n", Pins("L17"), Attrs(IOStandard="TMDS_33")),
Subsignal("hpd_notif", PinsN("R18"),
Attrs(IOStandard="LVCMOS33")), # Also called HDMI_HEAC_n
Subsignal("hdmi_heac_p", PinsN("T19"),
Attrs(IOStandard="LVCMOS33")),
Attrs(DRIVE=4),
),
Resource(
"lcd",
0,
Subsignal(
"db",
Pins("J3 H1 K4 J1 K3 K2 L4 K1 L3 L2 M4 L1 M3 M1 N4 N2 N3 N1"),
Attrs(IOStandard="LVCMOS33")),
Subsignal("rd", Pins("P2"), Attrs(IOStandard="LVCMOS33")),
Subsignal("wr", Pins("P4"), Attrs(IOStandard="LVCMOS33")),
Subsignal("rs", Pins("P1"), Attrs(IOStandard="LVCMOS33")),
Subsignal("cs", Pins("P3"), Attrs(IOStandard="LVCMOS33")),
Subsignal("id", Pins("J4"), Attrs(IOStandard="LVCMOS33")),
Subsignal("rst", Pins("H2"), Attrs(IOStandard="LVCMOS33")),
Subsignal("fmark", Pins("G1"), Attrs(IOStandard="LVCMOS33")),
Subsignal("blen", Pins("P5"), Attrs(IOStandard="LVCMOS33")),
),
Resource(
"spiflash",
0, # clock needs to be accessed through USRMCLK
Subsignal("cs_n", Pins("R2"), Attrs(IOStandard="LVCMOS33")),
Subsignal("mosi", Pins("W2"), Attrs(IOStandard="LVCMOS33")),
Subsignal("miso", Pins("V2"), Attrs(IOStandard="LVCMOS33")),
Subsignal("wp", Pins("Y2"), Attrs(IOStandard="LVCMOS33")),
Subsignal("hold", Pins("W1"), Attrs(IOStandard="LVCMOS33")),
),
Resource(
"spiflash4x",
0, # clock needs to be accessed through USRMCLK
Subsignal("cs_n", Pins("R2"), Attrs(IOStandard="LVCMOS33")),
Subsignal("dq", Pins("W2 V2 Y2 W1"), Attrs(IOStandard="LVCMOS33")),
),
Resource(
"spiram4x",
0,
Subsignal("cs_n", Pins("D20"), Attrs(IOStandard="LVCMOS33"),
Attrs(SLEWRATE="SLOW")),
Subsignal("clk", Pins("E20"), Attrs(IOStandard="LVCMOS33"),
Attrs(SLEWRATE="SLOW")),
Subsignal("dq", Pins("E19 D19 C20 F19"),
Attrs(IOStandard="LVCMOS33"), Attrs(PULLMODE="UP"),
Attrs(SLEWRATE="SLOW")),
),
Resource(
"spiram4x",
1,
Subsignal("cs_n", Pins("F20"), Attrs(IOStandard="LVCMOS33"),
Attrs(SLEWRATE="SLOW")),
Subsignal("clk", Pins("J19"), Attrs(IOStandard="LVCMOS33"),
Attrs(SLEWRATE="SLOW")),
Subsignal("dq", Pins("J20 G19 G20 H20"),
Attrs(IOStandard="LVCMOS33"), Attrs(PULLMODE="UP"),
Attrs(SLEWRATE="SLOW")),
),
Resource(
"sao",
0,
Subsignal("sda", Pins("B3")),
Subsignal("scl", Pins("B2")),
Subsignal("gpio", Pins("A2 A3 B4")),
Subsignal("drm", Pins("A4")),
),
Resource(
"sao",
1,
Subsignal("sda", Pins("A16")),
Subsignal("scl", Pins("B17")),
Subsignal("gpio", Pins("B18 A17 B16")),
Subsignal("drm", Pins("C17")),
),
Resource(
"testpts",
0,
Subsignal("a1", Pins("A15")),
Subsignal("a2", Pins("C16")),
Subsignal("a3", Pins("A14")),
Subsignal("a4", Pins("D16")),
Subsignal("b1", Pins("B15")),
Subsignal("b2", Pins("C15")),
Subsignal("b3", Pins("A13")),
Subsignal("b4", Pins("B13")),
),
Resource("sdram_clock", 0, Pins("D11"), Attrs(IOStandard="LVCMOS33")),
Resource(
"sdram", 0,
Subsignal("a",
Pins("A8 D9 C9 B9 C14 E17 A12 B12 H17 G18 B8 A11 B11")),
Subsignal("dq", Pins("C5 B5 A5 C6 B10 C10 D10 A9")),
Subsignal("we_n", Pins("B6")), Subsignal("ras_n", Pins("D6")),
Subsignal("cas_n", Pins("A6")), Subsignal("cs_n", Pins("C7")),
Subsignal("cke", Pins("C11")), Subsignal("ba", Pins("A7 C8")),
Subsignal("dm", Pins("A10")), Attrs(IOStandard="LVCMOS33"),
Attrs(SLEWRATE="FAST")),
# Compatibility.
Resource("user_io", 0, Pins("A15")),
Resource("user_io", 1, Pins("C16")),
Resource("user_io", 2, Pins("A14")),
Resource("user_io", 3, Pins("D16")),
]
connectors = [
Connector("pmod", 0, "A15 C16 A14 D16 B15 C15 A13 B13"),
Connector(
"genio", 0,
"C5 B5 A5 C6 B6 A6 D6 C7 A7 C8 B8 A8 D9 C9 B9 A9 D10 C10 B10 A10 D11 C11 B11 A11 G18 H17 B12 A12 E17 C14"
),
]
def __init__(self, *args, **kwargs):
logging.warning(
"This platform is not officially supported, and thus not tested.")
logging.warning("Your results may vary.")
super().__init__(*args, **kwargs)
def toolchain_prepare(self, fragment, name, **kwargs):
overrides = {'ecppack_opts': '--compress --freq 38.8'}
return super().toolchain_prepare(fragment, name, **overrides, **kwargs)
def toolchain_program(self, products, name):
""" Program the flash of an Supercon board. """
# Use the DFU bootloader to program the ECP5 bitstream.
dfu_util = os.environ.get("DFU_UTIL", "dfu-util")
with products.extract("{}.bit".format(name)) as bitstream_filename:
subprocess.check_call([
dfu_util, "-d", "1d50:614b", "-a", "0", "-D",
bitstream_filename
])
def toolchain_flash(self, products, name="top"):
""" Program the flash of an Supercon cartridge. """
# Use the DFU bootloader to program the ECP5 bitstream.
dfu_util = os.environ.get("DFU_UTIL", "dfu-util")
with products.extract("{}.bit".format(name)) as bitstream_filename:
subprocess.check_call([
dfu_util, "-d", "1d50:614b", "-a", "2", "-D",
bitstream_filename
])
class USB2SnifferPlatform(Xilinx7SeriesPlatform, LUNAPlatform):
""" Board description for OpenVizsla USB analyzer. """
name = "LambdaConcept USB2Sniffer"
device = "xc7a35t"
package = "fgg484"
speed = "1"
default_clk = "clk100"
# Provide the type that'll be used to create our clock domains.
clock_domain_generator = StubClockDomainGenerator
# We only have a single PHY; so use it directly.
default_usb_connection = "target_phy"
#
# I/O resources.
#
resources = [
Resource("clk100", 0, Pins("J19"), Attrs(IOStandard="LVCMOS33")),
Resource("led", 0, PinsN("W1"), Attrs(IOStandard="LVCMOS33")),
Resource("led", 1, PinsN("Y2"), Attrs(IOStandard="LVCMOS33")),
Resource(
"rgb_led",
0,
Subsignal("r", PinsN("W2")),
Subsignal("g", PinsN("Y1")),
Subsignal("b", PinsN("W1")),
Attrs(IOStandard="LVCMOS33"),
),
Resource(
"rgb_led",
1,
Subsignal("r", PinsN("AA1")),
Subsignal("g", PinsN("AB1")),
Subsignal("b", PinsN("Y2")),
Attrs(IOStandard="LVCMOS33"),
),
Resource(
"serial",
0,
Subsignal("tx", Pins("U21")), # FPGA_GPIO0
Subsignal("rx", Pins("T21")), # FPGA_GPIO1
Attrs(IOStandard="LVCMOS33"),
),
Resource(
"ddram",
0,
Subsignal("a",
Pins("M2 M5 M3 M1 L6 P1 N3 N2"
"M6 R1 L5 N5 N4 P2 P6"),
Attrs(IOStandard="SSTL15")),
Subsignal("ba", Pins("L3 K6 L4"), Attrs(IOStandard="SSTL15")),
Subsignal("ras_n", Pins("J4"), Attrs(IOStandard="SSTL15")),
Subsignal("cas_n", Pins("K3"), Attrs(IOStandard="SSTL15")),
Subsignal("we_n", Pins("L1"), Attrs(IOStandard="SSTL15")),
Subsignal("dm", Pins("G3 F1"), Attrs(IOStandard="SSTL15")),
Subsignal(
"dq", Pins("G2 H4 H5 J1 K1 H3 H2 J5"
"E3 B2 F3 D2 C2 A1 E2 B1"),
Attrs(IOStandard="SSTL15", IN_TERM="UNTUNED_SPLIT_50")),
Subsignal("dqs_p", Pins("K2 E1"), Attrs(IOStandard="DIFF_SSTL15")),
Subsignal("dqs_n", Pins("J2 D1"), Attrs(IOStandard="DIFF_SSTL15")),
Subsignal("clk_p", Pins("P5"), Attrs(IOStandard="DIFF_SSTL15")),
Subsignal("clk_n", Pins("P4"), Attrs(IOStandard="DIFF_SSTL15")),
Subsignal("cke", Pins("J6"), Attrs(IOStandard="SSTL15")),
Subsignal("odt", Pins("K4"), Attrs(IOStandard="SSTL15")),
Subsignal("reset_n", Pins("G1"), Attrs(IOStandard="SSTL15")),
Attrs(SLEW="FAST"),
),
Resource("flash", 0, Subsignal("cs_n", Pins("T19")),
Subsignal("mosi", Pins("P22")),
Subsignal("miso", Pins("R22")), Subsignal("vpp", Pins("P21")),
Subsignal("hold", Pins("R21")), Attrs(IOStandard="LVCMOS33")),
Resource("usb_fifo_clock", 0, Pins("D17"),
Attrs(IOStandard="LVCMOS33")),
Resource(
"usb_fifo", 0, Subsignal("rst", Pins("K22")),
Subsignal(
"data",
Pins(
"A16 F14 A15 F13 A14 E14 A13 E13 B13 C15 C13 C14 B16 E17 B15 F16"
"A20 E18 B20 F18 D19 D21 E19 E21 A21 B21 A19 A18 F20 F19 B18 B17"
)), Subsignal("be", Pins("K16 L16 G20 H20")),
Subsignal("rxf_n", Pins("M13")), Subsignal("txe_n", Pins("L13")),
Subsignal("rd_n", Pins("K19")), Subsignal("wr_n", Pins("M15")),
Subsignal("oe_n", Pins("L21")), Subsignal("siwua", Pins("M16")),
Attrs(IOStandard="LVCMOS33", SLEW="FAST")),
Resource(
"ulpi_sw",
0,
Subsignal("s", Pins("Y8", dir="o")),
Subsignal("oe", PinsN("Y9", dir="o")),
Attrs(IOStandard="LVCMOS33"),
),
# Host PHY -- connects directly to the host port.
ULPIResource("target_phy",
data_sites="AB18 AA18 AA19 AB20 AA20 AB21 AA21 AB22",
clk_site="W19",
dir_site="W21",
stp_site="Y22",
nxt_site="W22",
reset_site="V20",
attrs=Attrs(IOStandard="LVCMOS33", SLEW="FAST")),
# Target PHY -- connects via a switch to the target port.
ULPIResource("sideband_phy",
data_sites="AB2 AA3 AB3 Y4 AA4 AB5 AA5 AB6",
clk_site="V4",
dir_site="AB7",
stp_site="AA6",
nxt_site="AB8",
reset_site="AA8",
attrs=Attrs(IOStandard="LVCMOS33", SLEW="FAST"))
]
connectors = []
def toolchain_program(self, products, name):
xc3sprog = os.environ.get("XC3SPROG", "xc3sprog")
with products.extract("{}.bit".format(name)) as bitstream_file:
subprocess.check_call([xc3sprog, "-c", "ft4232h", bitstream_file])
class OpenVizsla(XilinxSpartan6Platform):
""" Board description for OpenVizsla USB analyzer. """
name = "OpenVizsla"
device = "xc6slx9"
package = "tqg144"
speed = "3"
default_clk = "clk_12MHz"
# Provide the type that'll be used to create our clock domains.
clock_domain_generator = StubClockDomainGenerator
# We only have a single PHY; so use it directly.
default_usb_connection = "target_phy"
#
# I/O resources.
#
resources = [
# Clocks.
Resource("clk_12MHz", 0, Pins("P50", dir="i"), Clock(12e6),
Attrs(IOSTANDARD="LVCMOS33")),
# User button.
Resource("btn", 0, Pins("P67", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
# User LEDs.
Resource("led", 0, Pins("P57", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("led", 1, Pins("P58", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("led", 2, Pins("P59", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
# Core ULPI PHY.
ULPIResource(
"target_phy",
data_sites="P120 P119 P118 P117 P116 P115 P114 P112",
clk_site="P123",
dir_site="P124",
nxt_site="P121",
stp_site="P126",
reset_site="P127",
),
# Extra pins that the OpenVizsla calls the "spare" pins.
Resource("spare", 2, Pins("P102"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 3, Pins("P101"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 4, Pins("P100"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 5, Pins("P99"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 6, Pins("P98"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 7, Pins("P97"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 8, Pins("P95"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 9, Pins("P94"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 10, Pins("P93"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 11, Pins("P92"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 12, Pins("P88"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 13, Pins("P87"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 14, Pins("P85"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 15, Pins("P84"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 16, Pins("P83"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 17, Pins("P82"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 18, Pins("P81"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 19, Pins("P80"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 20, Pins("P79"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 21, Pins("P78"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 22, Pins("P75"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 23, Pins("P74"), Attrs(IOSTANDARD="LVCMOS33")),
# FTDI FIFO connection.
Resource("ftdi", 0, Subsignal("clk", Pins("P51")),
Subsignal("d", Pins("P65 P62 P61 P46 P45 P44 P43 P48")),
Subsignal("rxf_n", Pins("P55")),
Subsignal("txe_n",
Pins("P70")), Subsignal("rd_n", Pins("P41")),
Subsignal("wr_n", Pins("P40")),
Subsignal("siwua_n", Pins("P66")),
Subsignal("oe_n", Pins("P38")),
Attrs(IOSTANDARD="LVCMOS33", SLEW="FAST")),
# Trigger in/out pins.
# There's nothing stopping these from being used as I/O, so we'll allow them to be used either way.
Resource("trigger_in", 0, Pins("P75"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("trigger_out", 0, Pins("P74"), Attrs(IOSTANDARD="LVCMOS33")),
]
# TODO: detail the Spare connector here?
connectors = []
def toolchain_program(self, products, name):
""" Programs the OpenVizsla's FPGA. """
try:
from openvizsla import OVDevice
from openvizsla.libov import HW_Init
except ImportError:
raise ImportError(
"pyopenvizsla is required to program OpenVizsla boards")
# Connect to our OpenVizsla...
device = OVDevice()
failed = device.ftdi.open()
if failed:
raise IOError("Could not connect to OpenVizsla!")
# ... and pass it our bitstream.
try:
with products.extract(f"{name}.bit") as bitstream_file:
HW_Init(device.ftdi, bitstream_file.encode('ascii'))
finally:
device.ftdi.close()