def elaborate(self, platform):
m = Module()
# Create our domains...
m.domains.usb = ClockDomain()
m.domains.usb_io = ClockDomain()
m.domains.fast = ClockDomain()
# ... and create our 12 MHz USB clock.
m.submodules.pll = Instance(
"SB_PLL40_CORE",
i_REFERENCECLK=ClockSignal("sync"),
i_RESETB=Const(1),
i_BYPASS=Const(0),
o_PLLOUTCORE=ClockSignal("usb"),
# Create a 24 MHz PLL clock...
p_FEEDBACK_PATH="SIMPLE",
p_DIVR=0,
p_DIVF=15,
p_DIVQ=5,
p_FILTER_RANGE=4,
# ... and divide it by half to get 12 MHz.
p_PLLOUT_SELECT="GENCLK_HALF")
# We'll use our 48MHz clock for everything _except_ the usb_io domain...
m.d.comb += [
ClockSignal("usb_io").eq(ClockSignal("sync")),
ClockSignal("fast").eq(ClockSignal("sync"))
]
return m
def elaborate(self, platform):
m = Module()
# Create our domains...
m.domains.sync = ClockDomain()
m.domains.usb = ClockDomain()
m.domains.usb_io = ClockDomain()
m.domains.fast = ClockDomain()
# ... create our 48 MHz IO and 12 MHz USB clock...
m.submodules.pll = Instance(
"SB_PLL40_2F_CORE",
i_REFERENCECLK=platform.request(platform.default_clk),
i_RESETB=Const(1),
i_BYPASS=Const(0),
o_PLLOUTCOREA=ClockSignal("sync"),
o_PLLOUTCOREB=ClockSignal("usb"),
# Create a 48 MHz PLL clock...
p_FEEDBACK_PATH="SIMPLE",
p_PLLOUT_SELECT_PORTA="GENCLK",
p_PLLOUT_SELECT_PORTB="SHIFTREG_0deg",
p_DIVR=0,
p_DIVF=47,
p_DIVQ=4,
p_FILTER_RANGE=1,
)
# We'll use our 48MHz clock for everything _except_ the usb domain...
m.d.comb += [
ClockSignal("usb_io").eq(ClockSignal("sync")),
ClockSignal("fast").eq(ClockSignal("sync"))
]
return m
def verify_itype(self, m):
sig = self.build_signal(m, "I", [(0, 6, "1001011"), (7, 11, "10000"),
(12, 14, "001"), (15, 19, "00010"),
(20, 31, "000110111111")])
i = IType("itype.z")
i.elaborate(m.d.comb, sig)
m.d.comb += Assert(i.opcode == Const(0b1001011, 7))
m.d.comb += Assert(i.rd == Const(0b10000, 5))
m.d.comb += Assert(i.funct3 == Const(1, 3))
m.d.comb += Assert(i.rs1 == Const(2, 5))
m.d.comb += Assert(i.imm == Const(0b000110111111, 12))
sig = self.build_signal(m, "I", [(0, 6, "1001011"), (7, 11, "10000"),
(12, 14, "001"), (15, 19, "00010"),
(20, 31, "100110111111")])
i = IType("itype.s")
i.elaborate(m.d.comb, sig)
m.d.comb += Assert(i.opcode == Const(0b1001011, 7))
m.d.comb += Assert(i.rd == Const(0b10000, 5))
m.d.comb += Assert(i.funct3 == Const(1, 3))
m.d.comb += Assert(i.rs1 == Const(2, 5))
m.d.comb += Assert(
i.imm == Const(0b11111111111111111111100110111111, 32))
# matcher
m.d.comb += Assert(i.match(opcode=0b1001011))
m.d.comb += Assert(i.match(rd=0b10000))
m.d.comb += Assert(i.match(funct3=1))
m.d.comb += Assert(i.match(rs1=2))
m.d.comb += Assert(i.match(imm=0b11111111111111111111100110111111))
# builder
i_builder_check = Signal(32)
i_builder_opcode = Signal(7)
i_builder_rd = Signal(5)
i_builder_funct3 = Signal(3)
i_builder_rs1 = Signal(5)
i_builder_imm = Signal(11)
built_itype = IType.build_i32(i_builder_opcode,
i_builder_rd,
i_builder_funct3,
i_builder_rs1,
i_builder_imm,
ensure_ints=False)
m.d.comb += i_builder_check.eq(built_itype)
i = IType("itype.s")
i.elaborate(m.d.comb, built_itype)
m.d.comb += Assert(i_builder_opcode == i.opcode)
m.d.comb += Assert(i_builder_rd == i.rd)
m.d.comb += Assert(i_builder_funct3 == i.funct3)
m.d.comb += Assert(i_builder_rs1 == i.rs1)
m.d.comb += Assert(i_builder_imm == i.imm[0:12])
return [
i_builder_check, i_builder_opcode, i_builder_rd, i_builder_funct3,
i_builder_rs1, i_builder_imm
]
def verify_jtype(self, m):
sig = self.build_signal(m, "U", [(0, 6, "1001011"), (7, 11, "10000"),
(12, 19, "00100010"), (20, 20, "1"),
(21, 30, "1011000111"),
(31, 31, "1")])
j = JType("jtype")
j.elaborate(m.d.comb, sig)
m.d.comb += Assert(j.opcode == Const(0b1001011, 7))
m.d.comb += Assert(j.rd == Const(0b10000, 5))
m.d.comb += Assert(
j.imm == Const(0b1111_1111_1111_0010_0010_1101_1000_1110, 32))
m.d.comb += Assert(j.match(opcode=0b1001011))
m.d.comb += Assert(j.match(opcode=0b1001010) == 0)
m.d.comb += Assert(j.match(rd=0b10000))
m.d.comb += Assert(j.match(rd=0b00001) == 0)
m.d.comb += Assert(
j.match(imm=0b1111_1111_1111_0010_0010_1101_1000_1110)
) #extra bits - sign ext
m.d.comb += Assert(j.match(imm=0b110100010110110001110) == 0)
m.d.comb += Assert(
j.match(opcode=0b1001011,
rd=0b10000,
imm=0b1111_1111_1111_0010_0010_1101_1000_1110))
j_builder_check = Signal(32)
j_builder_opcode = Signal(7)
j_builder_rd = Signal(5)
j_builder_imm = Signal(21)
m.d.comb += Assume(j_builder_imm[0] == 0)
built_jtype = JType.build_i32(opcode=j_builder_opcode,
rd=j_builder_rd,
imm=j_builder_imm)
m.d.comb += j_builder_check.eq(built_jtype)
j = JType("jtype.build")
j.elaborate(m.d.comb, built_jtype)
m.d.comb += Assert(j_builder_opcode == j.opcode)
m.d.comb += Assert(j_builder_rd == j.rd)
m.d.comb += Assert(j_builder_imm == j.imm[0:21])
j = JType("jtype.se")
j.elaborate(m.d.comb, Const(0x8000_0000, 32))
m.d.comb += Assert(j.imm[20] == 1)
m.d.comb += Assert(j.imm[31] == 1)
j = JType("jtype.ze")
j.elaborate(m.d.comb, Const(0x7FFF_FFFF, 32))
m.d.comb += Assert(j.imm[20] == 0)
m.d.comb += Assert(j.imm[31] == 0)
return [j_builder_check, j_builder_opcode, j_builder_rd, j_builder_imm]
def __init__(self, *, bus, handle_clocking=True):
"""
Parameters:
"""
# If this looks more like a ULPI bus than a UTMI bus, translate it.
if hasattr(bus, 'dir'):
self.utmi = UTMITranslator(ulpi=bus,
handle_clocking=handle_clocking)
self.bus_busy = self.utmi.busy
self.translator = self.utmi
self.always_fs = False
self.data_clock = 60e6
# If this looks more like raw I/O connections than a UTMI bus, create a pure-gatware
# PHY to drive the raw I/O signals.
elif hasattr(bus, 'd_n'):
self.utmi = GatewarePHY(io=bus)
self.bus_busy = Const(0)
self.translator = self.utmi
self.always_fs = True
self.data_clock = 12e6
# Otherwise, use it directly.
# Note that since a true UTMI interface has separate Tx/Rx/control
# interfaces, we don't need to care about bus 'busyness'; so we'll
# set it to a const zero.
else:
self.utmi = bus
self.bus_busy = Const(0)
self.translator = None
self.always_fs = True
self.data_clock = 12e6
#
# I/O port
#
self.connect = Signal()
self.low_speed_only = Signal()
self.full_speed_only = Signal()
self.frame_number = Signal(11)
self.microframe_number = Signal(3)
self.sof_detected = Signal()
self.new_frame = Signal()
self.reset_detected = Signal()
self.suspended = Signal()
self.tx_activity_led = Signal()
self.rx_activity_led = Signal()
#
# Internals.
#
self._endpoints = []
def __init__(self, shape, value=None, name=None):
self.shape = shape
self.name = name or tracer.get_var_name(depth=2, default="FixedPoint")
if value is None:
self.value = Signal(shape.signal_shape(), name=self.name)
elif isinstance(value, Value):
self.value = value
elif isinstance(value, (int, float)):
val = FixedPointConst(value=value, shape=shape)
self.value = Const(val.value, shape=val.shape.signal_shape())
else:
raise TypeError(f"cannot create FixedPointValue from {value}")
def populate_ulpi_registers(self, m):
""" Creates translator objects that map our control signals to ULPI registers. """
# Function control.
function_control = Cat(self.xcvr_select, self.term_select, self.op_mode, Const(0), ~self.suspend, Const(0))
self.add_composite_register(m, 0x04, function_control, reset_value=0b01000001)
# OTG control.
otg_control = Cat(
self.id_pullup, self.dp_pulldown, self.dm_pulldown, self.dischrg_vbus,
self.chrg_vbus, Const(0), Const(0), self.use_external_vbus_indicator
)
self.add_composite_register(m, 0x0A, otg_control, reset_value=0b00000110)
def verify_stype(self, m):
sig = self.build_signal(m, "S", [(0, 6, "1001011"), (7, 11, "10000"),
(12, 14, "001"), (15, 19, "00010"),
(20, 24, "00011"),
(25, 31, "0111111")])
s = SType("stype")
s.elaborate(m.d.comb, sig)
m.d.comb += Assert(s.opcode == Const(0b1001011, 7))
m.d.comb += Assert(s.funct3 == Const(1, 3))
m.d.comb += Assert(s.rs1 == Const(2, 5))
m.d.comb += Assert(s.rs2 == Const(3, 5))
m.d.comb += Assert(s.imm == Const(0b011111110000, 12))
return []
def elaborate(self, platform):
m = Module()
locked = Signal()
# Create our domains...
m.domains.sync = ClockDomain()
m.domains.usb = ClockDomain()
m.domains.usb_io = ClockDomain()
m.domains.fast = ClockDomain()
# ... create our 48 MHz IO and 12 MHz USB clock...
clk48 = Signal()
clk12 = Signal()
m.submodules.pll = Instance("SB_PLL40_2F_CORE",
i_REFERENCECLK = platform.request(platform.default_clk),
i_RESETB = Const(1),
i_BYPASS = Const(0),
o_PLLOUTCOREA = clk48,
o_PLLOUTCOREB = clk12,
o_LOCK = locked,
# Create a 48 MHz PLL clock...
p_FEEDBACK_PATH = "SIMPLE",
p_PLLOUT_SELECT_PORTA = "GENCLK",
p_PLLOUT_SELECT_PORTB = "SHIFTREG_0deg",
p_DIVR = 0,
p_DIVF = 47,
p_DIVQ = 4,
p_FILTER_RANGE = 1,
)
# ... and constrain them to their new frequencies.
platform.add_clock_constraint(clk48, 48e6)
platform.add_clock_constraint(clk12, 12e6)
# We'll use our 48MHz clock for everything _except_ the usb domain...
m.d.comb += [
ClockSignal("usb") .eq(clk12),
ClockSignal("sync") .eq(clk48),
ClockSignal("usb_io") .eq(clk48),
ClockSignal("fast") .eq(clk48),
ResetSignal("usb") .eq(~locked),
ResetSignal("sync") .eq(~locked),
ResetSignal("usb_io") .eq(~locked),
ResetSignal("fast") .eq(~locked)
]
return m
def verify_utype(self, m):
sig = self.build_signal(m, "U", [(0, 6, "1001011"), (7, 11, "10000"),
(12, 31, "00100010000110111111")])
u = UType("utype")
u.elaborate(m.d.comb, sig)
m.d.comb += Assert(u.opcode == Const(0b1001011, 7))
m.d.comb += Assert(u.rd == Const(0b10000, 5))
m.d.comb += Assert(
u.imm == Const(0b00100010000110111111000000000000, 32))
m.d.comb += Assert(u.match(opcode=0b1001011))
m.d.comb += Assert(u.match(rd=0b10000))
m.d.comb += Assert(u.match(imm=0b00100010000110111111000000000000))
m.d.comb += Assert(u.match(opcode=0b1011011) == 0)
m.d.comb += Assert(u.match(rd=0b11000) == 0)
m.d.comb += Assert(
u.match(imm=0b10100010000110111111000000000000) == 0)
m.d.comb += Assert(
u.match(opcode=0b1001011,
rd=0b10000,
imm=0b00100010000110111111000000000000))
u = UType("utype.sign")
u.elaborate(m.d.comb, Const(0x8000_0000, 32))
m.d.comb += Assert(u.imm[31] == 1)
u = UType("utype.trailzero")
u.elaborate(m.d.comb, Const(0xFFFF_FFFF, 32))
m.d.comb += Assert(u.imm.bit_select(0, 12) == 0)
u_builder_check = Signal(32)
u_builder_opcode = Signal(7)
u_builder_rd = Signal(5)
u_builder_imm = Signal(20)
m.d.comb += Assume(u_builder_imm[0:12] == 0)
built_utype = UType.build_i32(opcode=u_builder_opcode,
rd=u_builder_rd,
imm=u_builder_imm)
m.d.comb += u_builder_check.eq(built_utype)
u = UType("utype.build")
u.elaborate(m.d.comb, built_utype)
m.d.comb += Assert(u_builder_opcode == u.opcode)
m.d.comb += Assert(u_builder_rd == u.rd)
m.d.comb += Assert(Cat(Repl(0, 12), u_builder_imm[12:32]) == u.imm)
return [u_builder_check, u_builder_opcode, u_builder_rd, u_builder_imm]
def match(self,
opcode=None,
funct3=None,
rs1=None,
rs2=None,
imm=None) -> Value:
""" Build boolean expression that matches x against provided parts """
if type(imm) == int:
# TOOD: other types need it as well
assert imm.bit_length() <= 32, "imm must be 32 bit long"
assert imm % 2 == 0, "btype has 2-byte offset"
# TODO: check ~20 hi bits of imm == sigen ext
imm = imm & (2**32) - 1
subexpressions = []
if opcode is not None:
subexpressions.append(self.opcode.matches(opcode))
if funct3 is not None:
subexpressions.append(self.funct3.matches(funct3))
if rs1 is not None: subexpressions.append(self.rs1.matches(rs1))
if rs2 is not None: subexpressions.append(self.rs2.matches(rs2))
if imm is not None: subexpressions.append(self.imm.matches(imm))
if not subexpressions:
print("warning: no matches provided for btype.match")
return Const(1)
res = subexpressions.pop(0)
while subexpressions:
res = res & subexpressions.pop(0)
return res
def match(self,
opcode=None,
rd=None,
funct3=None,
rs1=None,
imm=None) -> Value:
""" Build boolean expression that matches x against provided parts """
if type(imm) == int:
assert imm.bit_length(
) <= 32, "imm must be 32 bit long(12 bits+signext)"
imm = imm & (2**32) - 1
subexpressions = []
if opcode is not None:
subexpressions.append(self.opcode.matches(opcode))
if rd is not None: subexpressions.append(self.rd.matches(rd))
if funct3 is not None:
subexpressions.append(self.funct3.matches(funct3))
if rs1 is not None: subexpressions.append(self.rs1.matches(rs1))
if imm is not None: subexpressions.append(self.imm.matches(imm))
if not subexpressions:
print("warning: no matches provided for itype.match")
return Const(1)
res = subexpressions.pop(0)
while subexpressions:
res = res & subexpressions.pop(0)
return res
def __init__(
self,
addr: int, # CSR's address
name: str, # CSR's name
layout: Layout # CSR's layout
) -> None:
mask = 0
offset = 0
fields = list()
for _name, _shape, _access in layout:
if not isinstance(_shape, int):
raise TypeError('Shape must be a flat int: {}'.format(_shape))
fields.append((_name, _shape))
if _access in [CSRAccess.WLRL, CSRAccess.WARL]:
_mask = (1 << _shape) - 1
mask = mask | (_mask << offset)
offset = offset + _shape
self.addr = addr
self.name = name
self.mask = Const(
mask) # using the same mask for read and write operations
# IO
self.read = Record(fields, name=self.name + '_r')
self.write = Record(fields, name=self.name + '_w')
self.we = Signal()
def __init__(self, ParityCheckMatrix, codeword_width):
#[PARAMETER] - codeword_width: Width of the output Codeword
self.codeword_width = int(codeword_width)
#[PARAMETER] - data_output_matrix_rows: Rows of the Generator Matrix
self.data_output_matrix_rows = int(len(ParityCheckMatrix))
#[CONSTANT] - parity_check_matrix: A parity check matrix constant
self.parity_check_matrix = Array([
Const(ParityCheckMatrix[_][0], unsigned(self.codeword_width))
for _ in range(self.data_output_matrix_rows)
])
#[INPUT] - start: The start signal to start the decoding process(codeword)
self.start = Signal(1)
#[INPUT] - data_input: The data to be encoded
self.data_input = Signal(codeword_width)
#[OUTPUT] - data_output: The result of each row parity check
self.data_output = Signal(self.data_output_matrix_rows, reset=0)
#[OUTPUT] - done: The done signal to indicate that the decoding process has stopped.
self.done = Signal(1, reset=0)
def __init__(self, GeneratorMatrix, codeword_width):
#[PARAMETER] - codeword_width: Width of the output Codeword
self.codeword_width = int(codeword_width)
#[PARAMETER] - data_input_length: Width of the data input
self.data_input_length = int(len(GeneratorMatrix))
#[CONSTANT] - gen_matrix: A generator matrix constant
self.gen_matrix = Array([
Const(GeneratorMatrix[_][0], unsigned(self.codeword_width))
for _ in range(self.data_input_length)
])
#[INPUT] - start: The start signal to start the encoding process(codeword)
self.start = Signal(1)
#[INPUT] - data_input: The data to be encoded
self.data_input = Signal(self.data_input_length)
#[OUTPUT] - data_output: The encoded data (codeword)
self.data_output = Signal(self.codeword_width, reset=0)
#[OUTPUT] - done: The done signal to indicate that encoding has completed.
self.done = Signal(1, reset=0)
def process_load(self, input_value):
lh_value = Signal(32)
comb = self.core.current_module.d.comb
bit_to_replicate=Mux(self.core.itype.funct3[2], Const(0,1), input_value[15])
comb += lh_value.eq(Cat(input_value[0:16], Repl(bit_to_replicate, 16)))
return lh_value
def __init__(self, divr, divf, divq, filter_range, **params):
params["divr"] = divr
params["divf"] = divf
params["divq"] = divq
params["filter_range"] = filter_range
if "feedback_path" not in params:
params["feedback_path"] = "SIMPLE"
if "pllout_select" not in params:
params["pllout_select"] = "GENCLK"
ports = {
"PACKAGEPIN": ("i", 1),
"EXTFEEDBACK": ("i", 1),
"DYNAMICDELAY": ("i", 1),
"LATCHINPUTVALUE": ("i", 1),
"SCLK": ("i", 1),
"SDI": ("i", 1),
"SDO": ("o", 1),
"RESETB": ("i", 1),
"LOCK": ("o", 1),
"PLLOUTCORE": ("o", 1),
"PLLOUTGLOBAL": ("o", 1),
}
required = ("PACKAGEPIN", )
default = {"RESETB": Const(1)}
super().__init__("SB_PLL40_PAD", params, ports, required, default)
def elaborate(self, platform):
m = Module()
# Create our domains...
m.domains.sync = ClockDomain()
m.domains.usb = ClockDomain()
m.domains.usb_io = ClockDomain()
m.domains.fast = ClockDomain()
# ... ensure our clock is never instantiated with a Global buffer.
platform.lookup(platform.default_clk).attrs['GLOBAL'] = False
# ... create our 48 MHz IO and 12 MHz USB clocks...
clk48 = Signal()
clk12 = Signal()
m.submodules.pll = Instance(
"SB_PLL40_2F_PAD",
i_PACKAGEPIN=platform.request(platform.default_clk, dir="i"),
i_RESETB=Const(1),
i_BYPASS=Const(0),
o_PLLOUTGLOBALA=clk48,
o_PLLOUTGLOBALB=clk12,
# Create a 48 MHz PLL clock...
p_FEEDBACK_PATH="SIMPLE",
p_PLLOUT_SELECT_PORTA="GENCLK",
p_PLLOUT_SELECT_PORTB="SHIFTREG_0deg",
p_DIVR=0,
p_DIVF=63,
p_DIVQ=4,
p_FILTER_RANGE=1,
)
# ... and constrain them to their new frequencies.
platform.add_clock_constraint(clk48, 48e6)
platform.add_clock_constraint(clk12, 12e6)
# We'll use our 48MHz clock for everything _except_ the usb domain...
m.d.comb += [
ClockSignal("usb_io").eq(clk48),
ClockSignal("fast").eq(clk48),
ClockSignal("sync").eq(clk48),
ClockSignal("usb").eq(clk12)
]
return m
def elaborate(self, comb: List[Statement], input: Signal):
comb += self.opcode.eq(input[0:7])
comb += self.funct3.eq(input[12:15])
comb += self.rs1.eq(input[15:20])
comb += self.rs2.eq(input[20:25])
comb += self.imm.eq(
Cat(Const(0, 1), input[8:12], input[25:31], input[7],
Repl(input[31], 20)))
def check(self, m: Module, instr: Value, data: FormalData):
m.d.comb += [
Assert(data.post_ccs == data.pre_ccs),
Assert(data.post_a == data.pre_a),
Assert(data.post_b == data.pre_b),
Assert(data.post_x == data.pre_x),
Assert(data.post_sp == data.pre_sp),
Assert(data.addresses_written == 0),
]
m.d.comb += [
Assert(data.addresses_read == 1),
Assert(data.read_addr[0] == data.plus16(data.pre_pc, 1)),
]
n = data.pre_ccs[Flags.N]
z = data.pre_ccs[Flags.Z]
v = data.pre_ccs[Flags.V]
c = data.pre_ccs[Flags.C]
offset = Signal(signed(8))
br = instr[:4]
take_branch = Array([
Const(1),
Const(0),
(c | z) == 0,
(c | z) == 1,
c == 0,
c == 1,
z == 0,
z == 1,
v == 0,
v == 1,
n == 0,
n == 1,
(n ^ v) == 0,
(n ^ v) == 1,
(z | (n ^ v)) == 0,
(z | (n ^ v)) == 1,
])
m.d.comb += offset.eq(data.read_data[0])
m.d.comb += Assert(
data.post_pc == Mux(take_branch[br], (data.pre_pc + 2 +
offset)[:16], (data.pre_pc +
2)[:16]))
def check(self, m: Module):
self.assert_cycles(m, 4)
data = self.assert_cycle_signals(m,
1,
address=self.data.pre_pc + 1,
vma=1,
rw=1,
ba=0)
self.assert_cycle_signals(m, 2, vma=0, ba=0)
self.assert_cycle_signals(m, 3, vma=0, ba=0)
n = self.data.pre_ccs[Flags.N]
z = self.data.pre_ccs[Flags.Z]
v = self.data.pre_ccs[Flags.V]
c = self.data.pre_ccs[Flags.C]
offset = Signal(signed(8))
br = self.instr[:4]
take_branch = Array([
Const(1),
Const(0),
(c | z) == 0,
(c | z) == 1,
c == 0,
c == 1,
z == 0,
z == 1,
v == 0,
v == 1,
n == 0,
n == 1,
(n ^ v) == 0,
(n ^ v) == 1,
(z | (n ^ v)) == 0,
(z | (n ^ v)) == 1,
])
m.d.comb += offset.eq(data)
target = Mux(take_branch[br], self.data.pre_pc + 2 + offset,
self.data.pre_pc + 2)
self.assert_registers(m, PC=target)
self.assert_flags(m)
def elaborate(self, platform):
m = Module()
ac = Signal(self.width + 1)
ac_next = Signal.like(ac)
temp = Signal.like(ac)
q1 = Signal(self.width)
q1_next = Signal.like(q1)
i = Signal(range(self.width))
# combinatorial
with m.If(ac >= self.y):
m.d.comb += [
temp.eq(ac - self.y),
Cat(q1_next, ac_next).eq(Cat(1, q1, temp[0:self.width - 1]))
]
with m.Else():
m.d.comb += [Cat(q1_next, ac_next).eq(Cat(q1, ac) << 1)]
# synchronized
with m.If(self.start):
m.d.sync += [self.valid.eq(0), i.eq(0)]
with m.If(self.y == 0):
m.d.sync += [self.busy.eq(0), self.dbz.eq(1)]
with m.Else():
m.d.sync += [
self.busy.eq(1),
self.dbz.eq(0),
Cat(q1,
ac).eq(Cat(Const(0, 1), self.x, Const(0, self.width)))
]
with m.Elif(self.busy):
with m.If(i == self.width - 1):
m.d.sync += [
self.busy.eq(0),
self.valid.eq(1),
i.eq(0),
self.q.eq(q1_next),
self.r.eq(ac_next >> 1)
]
with m.Else():
m.d.sync += [i.eq(i + 1), ac.eq(ac_next), q1.eq(q1_next)]
return m
def elaborate(self, platform):
i_onoff = self.note_in.i_data.onoff
i_channel = self.note_in.i_data.channel
i_note = self.note_in.i_data.note
i_velocity = self.note_in.i_data.velocity
o_vn_valid = self.voice_note_out.o_valid
o_vn_note = self.voice_note_out.o_data.note
o_vg_valid = self.voice_gate_out.o_valid
o_vg_gate = self.voice_gate_out.o_data.gate
o_vg_velocity = self.voice_gate_out.o_data.velocity
if self.channel is None:
channel_ok = True
else:
channel_ok = i_channel == self.channel
if self.use_velocity:
velocity = i_velocity
else:
velocity = Const(64)
m = Module()
m.d.comb += [
self.note_in.o_ready.eq(True),
]
with m.If(self.note_in.received()):
with m.If(channel_ok):
with m.If(i_onoff):
m.d.sync += [
o_vn_valid.eq(True),
o_vn_note.eq(i_note),
o_vg_valid.eq(True),
o_vg_gate.eq(True),
o_vg_velocity.eq(velocity),
]
with m.Elif(i_note == o_vn_note):
m.d.sync += [
o_vg_valid.eq(True),
o_vg_gate.eq(False),
o_vg_velocity.eq(velocity),
]
with m.Else():
with m.If(self.voice_note_out.sent()):
m.d.sync += [
o_vn_valid.eq(False),
]
with m.If(self.voice_gate_out.sent()):
m.d.sync += [
o_vg_valid.eq(False),
]
return m
def run_example(self):
""" Concrete example """
m = self.module
comb = m.d.comb
last = self.time[1]
now = self.time[0]
for (rs1, rs1_val, rd, imm, result) in self.examples():
rs1_value_matcher = (
last.r[rs1] == rs1_val) if rs1_val is not None else Const(1)
with m.If(
Const(1)
& last.at_instruction_start()
& last.itype.match(opcode=Opcode.OpImm,
funct3=self.funct3(),
rs1=rs1,
rd=rd,
imm=imm)
& rs1_value_matcher):
comb += Assert(now.r[rd] == result)
def verify_btype(self, m):
sig = self.build_signal(m, "B", [(0, 6, "1001011"), (7, 7, "1"),
(8, 11, "0000"), (12, 14, "001"),
(15, 19, "00010"), (20, 24, "00011"),
(25, 30, "011111"), (31, 31, "1")])
b = BType("btype")
b.elaborate(m.d.comb, sig)
m.d.comb += Assert(b.opcode == Const(0b1001011, 7))
m.d.comb += Assert(b.funct3 == Const(1, 3))
m.d.comb += Assert(b.rs1 == Const(2, 5))
m.d.comb += Assert(b.rs2 == Const(3, 5))
m.d.comb += Assert(
b.imm == Cat(Const(0b1101111100000, 13), Repl(1, 19)))
m.d.comb += Assert(b.match(opcode=0b1001011))
m.d.comb += Assert(b.match(rs1=2))
m.d.comb += Assert(b.match(rs2=3))
m.d.comb += Assert(b.match(funct3=1))
m.d.comb += Assert(b.match(imm=0b11111111111111111111101111100000))
m.d.comb += Assert(
b.match(opcode=0b1001011,
funct3=1,
rs1=2,
rs2=3,
imm=0b11111111111111111111101111100000))
m.d.comb += Assert(~b.match(opcode=0b1001011,
funct3=3,
rs1=1,
rs2=5,
imm=0b11111111111111111111101111100000))
b_builder_check = Signal(32)
b_builder_opcode = Signal(7)
b_builder_f3 = Signal(3)
b_builder_rs1 = Signal(5)
b_builder_rs2 = Signal(5)
b_builder_imm = Signal(13)
m.d.comb += Assume(b_builder_imm[0] == 0)
built_btype = BType.build_i32(opcode=b_builder_opcode,
funct3=b_builder_f3,
rs1=b_builder_rs1,
rs2=b_builder_rs2,
imm=b_builder_imm)
m.d.comb += b_builder_check.eq(built_btype)
b = BType("btype.build")
b.elaborate(m.d.comb, built_btype)
m.d.comb += Assert(b_builder_opcode == b.opcode)
m.d.comb += Assert(b_builder_imm == Cat(Const(0, 1), b.imm[1:13]))
m.d.comb += Assert(b.imm[13:32] == Repl(b_builder_imm[12], 32 - 13))
return [
b_builder_check, b_builder_opcode, b_builder_f3, b_builder_rs1,
b_builder_rs2, b_builder_imm
]
def elaborate(self, platform):
m = Module()
locked = Signal()
# Create our domains...
m.domains.sync = ClockDomain()
m.domains.pol = ClockDomain()
# clocks 50 MHz circuit
# 1 MHz update frequency motor
clk50 = Signal()
# clk1 = Signal()
# details see iCE40 sysCLOCK PLL Design and Usage
# settings comment out are for SB_PLL40_2F_CORE
m.submodules.pll = \
Instance("SB_PLL40_CORE",
i_REFERENCECLK=platform.request(platform.default_clk),
i_RESETB=Const(1),
# i_BYPASS=Const(0),
o_PLLOUTGLOBAL=clk50,
o_LOCK=locked,
# Create a 50 MHz PLL clock...
p_FEEDBACK_PATH="SIMPLE",
# internally generated PLL
# p_PLLOUT_SELECT_PORTA="GENCLK",
# p_PLLOUT_SELECT_PORTB="SHIFTREG_0deg",
p_DIVR=0,
p_DIVF=7,
p_DIVQ=4,
p_FILTER_RANGE=5,
)
# ... and constrain them to their new frequencies.
platform.add_clock_constraint(clk50, 50e6)
# platform.add_clock_constraint(clk1, 1e6)
# We'll use our 50MHz clock for everything _except_ the polynomal
# which create ticks for the motors
m.d.comb += [
# ClockSignal("pol").eq(clk1),
ClockSignal("sync").eq(clk50),
# ResetSignal("pol").eq(~locked),
ResetSignal("sync").eq(~locked),
]
return m
def synth(core, m: Module):
with m.If(core.cycle == 1):
m.d.comb += core.alu.oper.eq(Operation.NOP)
m.d.sync += [
core.reg.PC.eq(add16(core.reg.PC, 1)),
core.enable.eq(1),
core.addr.eq(add16(core.reg.PC, 1)),
core.RWB.eq(1),
core.cycle.eq(2),
]
with m.If(core.cycle == 2):
m.d.comb += core.alu.oper.eq(Operation.NOP)
m.d.sync += [
core.tmp.eq(core.dout),
core.reg.PC.eq(add16(core.reg.PC, 1)),
core.enable.eq(1),
core.addr.eq(add16(core.reg.PC, 1)),
core.RWB.eq(1),
core.cycle.eq(3),
]
with m.If(core.cycle == 3):
m.d.comb += core.alu.oper.eq(Operation.NOP)
m.d.sync += [
core.reg.PC.eq(core.reg.PC),
core.enable.eq(1),
core.addr.eq(Cat(core.tmp, core.dout)),
core.RWB.eq(1),
core.cycle.eq(4),
]
with m.If(core.cycle == 4):
m.d.comb += [
core.alu.inputa.eq(core.dout),
core.alu.inputb.eq(Const(0x00)),
core.alu.oper.eq(Operation.OOR),
]
m.d.sync += [
core.reg.A.eq(core.alu.result),
core.reg.PC.eq(add16(core.reg.PC, 1)),
core.enable.eq(1),
core.addr.eq(add16(core.reg.PC, 1)),
core.RWB.eq(1),
core.cycle.eq(1),
]
def verify_rtype(self, m):
sig = self.build_signal(m, "R", [(0, 6, "1001011"), (7, 11, "10000"),
(12, 14, "001"), (15, 19, "00010"),
(20, 24, "00011"),
(25, 31, "0111111")])
r = RType("rtype")
r.elaborate(m.d.comb, sig)
m.d.comb += Assert(r.opcode == Const(0b1001011, 7))
m.d.comb += Assert(r.rd == Const(0b10000, 5))
m.d.comb += Assert(r.funct3 == Const(1, 3))
m.d.comb += Assert(r.rs1 == Const(2, 5))
m.d.comb += Assert(r.rs2 == Const(3, 5))
m.d.comb += Assert(r.funct7 == Const(0b0111111, 7))
return []
def elaborate(self, platform):
m = Module()
if platform is not None:
# platform.default_clk_frequency is in Hz
coeff = self._calc_freq_coefficients(
platform.default_clk_frequency / 1_000_000, self.freq_out)
# clk_pin = platform.request(platform.default_clk)
lock = Signal()
pll = Instance(
"SB_PLL40_CORE",
p_FEEDBACK_PATH='SIMPLE',
p_DIVR=coeff.divr,
p_DIVF=coeff.divf,
p_DIVQ=coeff.divq,
p_FILTER_RANGE=0b001,
p_DELAY_ADJUSTMENT_MODE_FEEDBACK='FIXED',
p_FDA_FEEDBACK=0b0000,
p_DELAY_ADJUSTMENT_MODE_RELATIVE='FIXED',
p_FDA_RELATIVE=0b0000,
p_SHIFTREG_DIV_MODE=0b00,
p_PLLOUT_SELECT='GENCLK',
p_ENABLE_ICEGATE=0b0,
i_REFERENCECLK=ClockSignal(),
o_PLLOUTCORE=ClockSignal(self.domain_name),
i_RESETB=ResetSignal(),
i_BYPASS=Const(0),
o_LOCK=lock,
)
rs = ResetSynchronizer(~lock, domain=self.domain_name)
m.submodules += [pll, rs]
m.domains += ClockDomain(self.domain_name)
return m
def __init__(self, *, bus, handle_clocking=True):
"""
Parameters:
"""
# If this looks more like a ULPI bus than a UTMI bus, translate it.
if not hasattr(bus, 'rx_valid'):
self.utmi = UTMITranslator(ulpi=bus, handle_clocking=handle_clocking)
self.bus_busy = self.utmi.busy
self.translator = self.utmi
# Otherwise, use it directly.
# Note that since a true UTMI interface has separate Tx/Rx/control
# interfaces, we don't need to care about bus 'busyness'; so we'll
# set it to a const zero.
else:
self.utmi = bus
self.bus_busy = Const(0)
self.translator = None
#
# I/O port
#
self.connect = Signal()
self.low_speed_only = Signal()
self.full_speed_only = Signal()
self.frame_number = Signal(11)
self.sof_detected = Signal()
self.suspended = Signal()
self.tx_activity_led = Signal()
self.rx_activity_led = Signal()
#
# Internals.
#
self._endpoints = []
