return m
if __name__ == '__main__':
duration = 3
design = OneShot(duration)
# work aroun nMigen bug #280
m = Module()
m.submodules.design = design
i_trg = Signal.like(design.i_trg)
m.d.comb += [
design.i_trg.eq(i_trg),
]
#280 with Main(design).sim as sim:
with Main(m).sim as sim:
@sim.sync_process
def test_proc():
def set(value):
#280 yield design.i_trg.eq(value)
yield i_trg.eq(value)
def chk(expected):
actual = yield design.o_pulse
assert actual == expected, f'wanted {expected}, got {actual}'
def chk_n(expected, n):
for _ in range(n):
yield from chk(expected)
yield
def __init__(self):
self.trigger = Signal()
def elaborate(self, platform):
m = Module()
src = TestSource()
snk = TestSink()
m.submodules.source = src
m.submodules.sink = self.sink = snk
m.d.comb += src.data_out.flow_to(snk.data_in)
m.d.comb += src.trigger.eq(self.trigger)
return m
top = Top()
with Main(top).sim as sim:
@sim.sync_process
def trigger_proc():
trg = top.trigger
for i in range(10):
yield trg.eq(True)
yield
if i % 3:
yield trg.eq(False)
yield from delay((i + 1) % 3)
yield trg.eq(False)
yield from delay(3)
@sim.sync_process
def result_proc():
expected = (
0, 0, 0,
m.d.sync += [
self.saw_out.o_valid.eq(False),
]
return m
if __name__ == '__main__':
divisor = 25
cfg = SynthConfig(1_000_000, divisor)
cfg.describe()
design = Oscillator(cfg)
design.note_in.leave_unconnected()
design.pulse_out.leave_unconnected()
design.saw_out.leave_unconnected()
with Main(design).sim as sim:
@sim.sync_process
def note_proc():
# from C5 to C7 by major thirds:
for note in range(60 + 12, 60 + 36 + 1, 4):
pw = (50 * note - 360) % 128
print(f'note = {note}, pw = {pw}')
yield design.pw_in.eq(pw)
yield design.note_in.i_valid.eq(True)
yield design.note_in.i_data.note.eq(note)
for _ in range(200):
yield
yield from delay(divisor - 1)
yield design.note_in.i_valid.eq(False)