def regmove(self, args):
destreg = args[0]
srcreg = args[1]
return opcodes.aluop("PASSB", destreg, srcreg)
def eventmove(self, args):
destreg = args[0]
srcreg = args[1]
print "Eventmove", destreg, srcreg
return opcodes.aluop("PASSA", destreg, srcreg, True, eaddr=srcreg)
def nop(self, args):
""" NO OP -- eats a tick """
return opcodes.aluop("PASSA", 0, 0)
def swapbytes(self, args):
destreg = args[0]
srcreg = args[1]
return opcodes.aluop("SWAPB", destreg, srcreg)
def subc(self, args):
destreg = args[0]
srcreg = args[1]
return opcodes.aluop("SUBC", destreg, srcreg)
def addc(self, args):
destreg = args[0]
srcreg = args[1]
return opcodes.aluop("ADDC", destreg, srcreg)
#!/usr/bin/python
import sys
sys.path.append("../../assemble")
import opcodes
oplist = []
#load R0 with 0x1234
oplist.append( opcodes.immop("PASSB", 0x34, 0))
oplist.append( opcodes.immop("MOVBTOHLOW", 0x12, 0))
#load R1 with 0x5678
oplist.append( opcodes.immop("PASSB", 0x78, 1))
oplist.append( opcodes.immop("MOVBTOHLOW", 0x56, 1))
# Try a simple move from reg 1 to reg 2:
oplist.append( opcodes.aluop("PASSB", 2, 1))
# try to swap the bytes
oplist.append( opcodes.aluop("SWAPB", 3, 2))
# complex logic
#load R5 with 0xF0F0
oplist.append( opcodes.immop("PASSB", 0xF0, 5))
oplist.append( opcodes.immop("MOVBTOHLOW", 0xF0, 5))
# and them
oplist.append( opcodes.aluop("AANDB", 5, 0) )
#load R6 with 0xF0F0
oplist.append( opcodes.immop("PASSB", 0xF0, 6))
oplist.append( opcodes.immop("MOVBTOHLOW", 0xF0, 6))
# or them
oplist.append( opcodes.aluop("AORB", 6, 0) )
# now test the event interface
#
# load Eaddr0 to register 7
oplist.append( opcodes.aluop("PASSA", 7, 0, True, 0))
