def test_NOTI_rx(): #Set RX to NOT HHLL chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address + 0, 0xE0) #op code chip16.write_8bit(initial_address + 1, 0b00000001) #y,x chip16.write_8bit(initial_address + 2, 0b11001100) #ll chip16.write_8bit(initial_address + 3, 0b00110011) #hh chip16.write_8bit(initial_address + 4, 0xE0) #op code chip16.write_8bit(initial_address + 5, 0b00000001) #y,x chip16.write_8bit(initial_address + 6, 0b11111111) #ll chip16.write_8bit(initial_address + 7, 0b11111111) #hh chip16.r[0x1] = 0xFACA chip16.step() chip16.r[0x1].should.be.eql(0b1100110000110011) chip16.r[0x1].should_not.be.eql(0xFACA) chip16.flag_zero.should.be.eql(0) chip16.flag_negative.should.be.eql(1) chip16.step() chip16.r[0x1].should.be.eql(0b0) chip16.flag_zero.should.be.eql(1) chip16.flag_negative.should.be.eql(0)
def test_NOT_rx_ry(): #Set RX to NOT RY chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address + 0, 0xE2) #op code chip16.write_8bit(initial_address + 1, 0b00000011) #y,x chip16.write_8bit(initial_address + 2, 0b0) #ll chip16.write_8bit(initial_address + 3, 0b0) #hh chip16.write_8bit(initial_address + 4, 0xE2) #op code chip16.write_8bit(initial_address + 5, 0b00000011) #y,x chip16.write_8bit(initial_address + 6, 0b0) #ll chip16.write_8bit(initial_address + 7, 0b0) #hh chip16.r[0b0] = 0b0011001111001100 chip16.step() chip16.r[0b11].should.be.eql(0b1100110000110011) chip16.flag_zero.should.be.eql(0) chip16.flag_negative.should.be.eql(1) chip16.r[0b0] = 0b1111111111111111 chip16.step() chip16.r[0b11].should.be.eql(0b0) chip16.flag_zero.should.be.eql(1) chip16.flag_negative.should.be.eql(0)
def test_FLIP(): # FLIP [0|1], [0|1] - Set hflip = [false|true], vflip = [false|true] chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address, 0x08) #op code chip16.write_8bit(initial_address + 1, 0x0) #x,y index operand chip16.write_8bit(initial_address + 2, 0x0) #ll operand chip16.write_8bit(initial_address + 3, 0b00) #hh operand chip16.step() chip16.gpu.hflip.should.be.falsy chip16.gpu.vflip.should.be.falsy chip16.write_8bit(initial_address + 4, 0x08) #op code chip16.write_8bit(initial_address + 5, 0x0) #x,y index operand chip16.write_8bit(initial_address + 6, 0x0) #ll operand chip16.write_8bit(initial_address + 7, 0b01) #hh operand chip16.step() chip16.gpu.hflip.should.be.falsy chip16.gpu.vflip.should.be.truthy chip16.write_8bit(initial_address + 8, 0x08) #op code chip16.write_8bit(initial_address + 9, 0x0) #x,y index operand chip16.write_8bit(initial_address + 10, 0x0) #ll operand chip16.write_8bit(initial_address + 11, 0b11) #hh operand chip16.step() chip16.gpu.hflip.should.be.truthy chip16.gpu.vflip.should.be.truthy
def test_POP_rx(): #Decrease SP by 2, set RX to [SP] chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address #PUSH chip16.write_8bit(initial_address + 0, 0xC0) #op code chip16.write_8bit(initial_address + 1, 0b00110001) #y,x chip16.write_8bit(initial_address + 2, 0x0) #ll chip16.write_8bit(initial_address + 3, 0x0) #hh #POP chip16.write_8bit(initial_address + 4, 0xC1) #op code chip16.write_8bit(initial_address + 5, 0b00100011) #y,x chip16.write_8bit(initial_address + 6, 0x0) #ll chip16.write_8bit(initial_address + 7, 0x0) #hh chip16.r[0x1] = 0xFFAA original_sp = chip16.sp chip16.step() chip16.step() chip16.sp.should.be.eql(original_sp) chip16.r[0x3].should.be.eql(0xFFAA)
def test_DRW_RZ_with_overlaps(): # Draw sprite from [RZ] at (RX, RY). gpu = Mock() gpu.there_is_overlap = Mock(return_value=True) gpu.drw_rz = Mock(return_value=1) chip16 = cpu.Cpu() chip16.gpu = gpu initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address, 0x06) #op code chip16.write_8bit(initial_address + 1, 0b00010010) #x,y index operand chip16.write_8bit(initial_address + 2, 0b00000011) #ll operand chip16.write_8bit(initial_address + 3, 0x42) #hh operand chip16.r[0b0001] = 0x10 #y chip16.r[0b0010] = 0x20 #x chip16.r[0b0011] = 0x4000 #z => pointing to address 0x4000 chip16.write_8bit(0x4000, 0xAA) chip16.write_8bit(0x4001, 0xBB) chip16.step() # we need to compare both using 2's complement gpu.drw_rz.assert_called_once_with(0xBBAA, 0x20, 0x10) chip16.flag_carry.should.eql(0x1)
def test_RET(): # Decrease SP by 2, set PC to [SP]. chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address, 0x14) #op code chip16.write_8bit(initial_address + 1, 0x00) #y,x chip16.write_8bit(initial_address + 2, 0xBB) #hh chip16.write_8bit(initial_address + 3, 0x10) #ll chip16.write_8bit(0x10BB + 0, 0x15) chip16.write_8bit(0x10BB + 1, 0x0) chip16.write_8bit(0x10BB + 2, 0x0) chip16.write_8bit(0x10BB + 3, 0x0) chip16.step() chip16.sp.should.be.eql(chip16.STACK_START + 2) chip16.read_8bit(chip16.sp - 2).should.be.eql(initial_address + 4) chip16.pc.should.be.eql(0x10BB) chip16.step() chip16.pc.should.be.eql(initial_address + 4)
def test_general_registers(): chip16 = cpu.Cpu() for r in range(0x0, 0xF): chip16.r[r] = 0x00FA chip16.r[0x0].should.eql(0x00FA) chip16.r[0xF - 1].should.eql(0x00FA)
def test_little_endianess(): chip16 = cpu.Cpu() chip16.write_16bit(0x0000, 0x00AA) chip16.read_8bit(0x0000).should.eql(0x00AA) chip16.read_8bit(0x0001).should.eql(0x0000) hex(chip16.read_8bit(0x0000)).should.eql("0xaa")
def test_write_and_read(): chip16 = cpu.Cpu() cafe = 0xCAFE chip16.write_16bit(0x0000, cafe) chip16.read_8bit(0x0000).should.eql(0xFE) chip16.read_8bit(0x0001).should.eql(0xCA) chip16.read_16bit(0x0000).should.eql(0xCAFE)
def test_CALL_x(): #If x, then perform a CALL. chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address, 0x17) #op code chip16.write_8bit(initial_address + 1, 0b00000001) #y,x chip16.write_8bit(initial_address + 2, 0xFA) #ll chip16.write_8bit(initial_address + 3, 0xCA) #hh chip16.step() chip16.pc.should.be.eql(0xCAFA)
def test_JMP(): # Set PC to HHLL. chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address, 0x10) #op code chip16.write_8bit(initial_address + 1, 0x33) #AD chip16.write_8bit(initial_address + 2, 0xBB) #sr operand chip16.write_8bit(initial_address + 3, 0x10) #vt operand chip16.step() chip16.pc.should.be.eql(0x10BB)
def test_NOP(): # NOP - No operation. chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address, 0x00) #op code chip16.write_8bit(initial_address + 1, 0x00) #x,y index operand chip16.write_8bit(initial_address + 2, 0x00) #ll operand chip16.write_8bit(initial_address + 3, 0x00) #hh operand chip16.step() chip16.current_cyles.should.eql(1) chip16.pc.should.eql(initial_address + 4)
def test_LDI_SP(): # LDI SP, HHLL chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address, 0x21) #op code chip16.write_8bit(initial_address + 1, 0b00010000) #x,y index operand chip16.write_8bit(initial_address + 2, 0xFF) #ll operand chip16.write_8bit(initial_address + 3, 0xAA) #hh operand chip16.step() chip16.sp.should.eql(0xAAFF) chip16.current_cyles.should.eql(1) chip16.pc.should.eql(initial_address + 4)
def test_BGC(): # BGC N - Set background color to index N (0 is black). chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address, 0x03) #op code chip16.write_8bit(initial_address + 1, 0x00) #x,y index operand chip16.write_8bit(initial_address + 2, 0b00000100) #ll operand chip16.write_8bit(initial_address + 3, 0x00) #hh operand chip16.step() chip16.current_cyles.should.eql(1) chip16.pc.should.eql(initial_address + 4) chip16.gpu.bg.should.eql(0b0100)
def test_SNG(): # Set sound generation parameters. spu = Mock() chip16 = cpu.Cpu() chip16.spu = spu initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address, 0x0E) #op code chip16.write_8bit(initial_address + 1, 0x33) #AD chip16.write_8bit(initial_address + 2, 0xBB) #sr operand chip16.write_8bit(initial_address + 3, 0x10) #vt operand chip16.step() spu.setup.assert_called_once_with(0x33, 0x10BB)
def test_SND3(): # Play 1500Hz tone for HHLL ms. spu = Mock() chip16 = cpu.Cpu() chip16.spu = spu initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address, 0x0C) #op code chip16.write_8bit(initial_address + 1, 0x0) #x,y index operand chip16.write_8bit(initial_address + 2, 0xBB) #ll operand chip16.write_8bit(initial_address + 3, 0x10) #hh operand chip16.step() spu.play1500hz.assert_called_once_with(0x10BB)
def test_SHR_rx(): #Set RX to RX >> N chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address, 0xB1) #op code chip16.write_8bit(initial_address + 1, 0b00000001) #y,x chip16.write_8bit(initial_address + 2, 0x3) #ll chip16.write_8bit(initial_address + 3, 0x0) #hh chip16.r[0x1] = 0b10000 chip16.step() chip16.r[0x1].should.be.eql(0b10)
def test_NEG_rx_hhll(): #Set RX to NEG HHLL chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address + 0, 0xE3) #op code chip16.write_8bit(initial_address + 1, 0b00000011) #y,x chip16.write_8bit(initial_address + 2, 0x02) #ll chip16.write_8bit(initial_address + 3, 0x00) #hh chip16.step() chip16.r[0b11].should.be.eql(-2) chip16.flag_zero.should.be.eql(0) chip16.flag_negative.should.be.eql(1)
def test_CALL(): # Store PC to [SP], increase SP by 2, set PC to HHLL. chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address, 0x14) #op code chip16.write_8bit(initial_address + 1, 0x00) #y,x chip16.write_8bit(initial_address + 2, 0xBB) #hh chip16.write_8bit(initial_address + 3, 0x10) #ll chip16.step() chip16.sp.should.be.eql(chip16.STACK_START + 2) chip16.read_8bit(chip16.sp - 2).should.be.eql(initial_address + 4) chip16.pc.should.be.eql(0x10BB)
def test_JME(): #Set PC to HHLL if RX == RY. chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address, 0x13) #op code chip16.write_8bit(initial_address + 1, 0b00010010) #y,x chip16.write_8bit(initial_address + 2, 0xBB) #hh chip16.write_8bit(initial_address + 3, 0x10) #ll chip16.r[1] = chip16.r[2] = 0xF chip16.step() chip16.pc.should.be.eql(0x10BB)
def test_SND0(): # Stop playing sounds. spu = Mock() chip16 = cpu.Cpu() chip16.spu = spu initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address, 0x09) #op code chip16.write_8bit(initial_address + 1, 0x0) #x,y index operand chip16.write_8bit(initial_address + 2, 0x0) #ll operand chip16.write_8bit(initial_address + 3, 0x0) #hh operand chip16.step() spu.stop.assert_called_once()
def test_TSTI(): #Compute RX&HHLL, discard result. chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address, 0x63) #op code chip16.write_8bit(initial_address + 1, 0b00100001) #y,x chip16.write_8bit(initial_address + 2, 0b00000000) #ll chip16.write_8bit(initial_address + 3, 0b00000000) #hh chip16.r[0x1] = 0b00000111 chip16.step() chip16.flag_zero.should.be.eql(0x1)
def test_MODI(): #Set RX to RX MOD HHLL chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address, 0xA3) #op code chip16.write_8bit(initial_address + 1, 0b00100001) #y,x chip16.write_8bit(initial_address + 2, 0x3) #ll chip16.write_8bit(initial_address + 3, 0x0) #hh chip16.r[0x1] = 0x4 chip16.step() chip16.r[0x1].should.be.eql(0x4 % 0x3)
def test_ANDi(): #Set RX to RX&HHLL. chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address, 0x60) #op code chip16.write_8bit(initial_address + 1, 0b00100001) #y,x chip16.write_8bit(initial_address + 2, 0b00000010) #ll chip16.write_8bit(initial_address + 3, 0b00000000) #hh chip16.r[0x1] = 0b00000111 chip16.step() chip16.r[0x1].should.be.eql(0b00000010)
def test_ADDI_rx(): #Set RX to RX+HHLL. chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address, 0x40) #op code chip16.write_8bit(initial_address + 1, 0b00000001) #y,x chip16.write_8bit(initial_address + 2, 0x03) #ll chip16.write_8bit(initial_address + 3, 0x00) #hh chip16.r[0x1] = 0x3 chip16.step() chip16.r[0x1].should.be.eql(0x6)
def test_JMP_RX(): #Set PC to RX. chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address, 0x16) #op code chip16.write_8bit(initial_address + 1, 0x00) #y,x chip16.write_8bit(initial_address + 2, 0x00) #hh chip16.write_8bit(initial_address + 3, 0x00) #ll chip16.r[0x0] = 0xFACA chip16.step() chip16.pc.should.be.eql(0xFACA)
def test_PUSHALL_and_POPALL(): #Store R0..RF at [SP], increase SP by 32 #Decrease SP by 32, load R0..RF from [SP] chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address #PUSHALL chip16.write_8bit(initial_address + 0, 0xC2) #op code chip16.write_8bit(initial_address + 1, 0x0) #y,x chip16.write_8bit(initial_address + 2, 0x0) #ll chip16.write_8bit(initial_address + 3, 0x0) #hh #POPALL chip16.write_8bit(initial_address + 4, 0xC3) #op code chip16.write_8bit(initial_address + 5, 0x0) #y,x chip16.write_8bit(initial_address + 6, 0x0) #ll chip16.write_8bit(initial_address + 7, 0x0) #hh original_sp = chip16.sp #random values to each register for x in range(0x0, 0xF + 1): chip16.r[x] = random.randint(0x0000, 0xFFFF) chip16.step() original_r0 = chip16.r[0x0] original_r1 = chip16.r[0x1] original_rf = chip16.r[0xF] chip16.sp.should.be.eql(original_sp + 32) chip16.read_16bit(original_sp).should.be.eql(original_r0) chip16.read_16bit(original_sp + 2).should.be.eql(original_r1) chip16.read_16bit(original_sp + 30).should.be.eql(original_rf) #another turn of random values to each register for x in range(0x0, 0xF + 1): chip16.r[x] = random.randint(0x0000, 0xFFFF) chip16.step() chip16.sp.should.be.eql(original_sp) chip16.r[0x0].should.be.eql(original_r0) chip16.r[0x1].should.be.eql(original_r1) chip16.r[0xF].should.be.eql(original_rf)
def test_AND_rz(): #Set RZ to RX&RY. chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address, 0x62) #op code chip16.write_8bit(initial_address + 1, 0b00100001) #y,x chip16.write_8bit(initial_address + 2, 0b00000011) #ll chip16.write_8bit(initial_address + 3, 0b00000000) #hh chip16.r[0x1] = 0b00000111 chip16.r[0x2] = 0b00000101 chip16.step() chip16.r[0x3].should.be.eql(0b00000101)
def test_SUB_rx_ry(): #Set RX to RX-RY. chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address, 0x51) #op code chip16.write_8bit(initial_address + 1, 0b00100001) #y,x chip16.write_8bit(initial_address + 2, 0x1) #ll chip16.write_8bit(initial_address + 3, 0x00) #hh chip16.r[0x1] = 0x2 chip16.r[0x2] = 0x2 chip16.step() chip16.r[0x1].should.be.eql(0x0)
def test_SPR(): # SPR HHLL - Set sprite width (LL) and height (HH). chip16 = cpu.Cpu() initial_address = 0x0000 chip16.pc = initial_address chip16.write_8bit(initial_address, 0x04) #op code chip16.write_8bit(initial_address + 1, 0x00) #x,y index operand chip16.write_8bit(initial_address + 2, 0x21) #ll operand chip16.write_8bit(initial_address + 3, 0x42) #hh operand chip16.step() chip16.current_cyles.should.eql(1) chip16.pc.should.eql(initial_address + 4) chip16.gpu.spritew.should.eql(0x21) chip16.gpu.spriteh.should.eql(0x42)