def run_test(model, test_vectors):
# Instantiate and elaborate the model
model.elaborate()
# Define functions mapping the test vector to ports in model
def tv_in(model, test_vector):
model.reqs.value = test_vector[0]
def tv_out(model, test_vector):
assert model.grants == test_vector[1]
# Run the test
sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
sim.run_test()
def test_1entry_skid( dump_vcd, test_verilog ):
"""Single Element Skid Queue."""
test_vectors = [
# Enqueue one element and then dequeue it
# enq.val enq.rdy enq.bits deq.val deq.rdy deq.bits
[ 1, 1, 0x0001, 1, 1, 0x0001 ],
[ 1, 0, 0x0006, 1, 0, 0x0001 ],
[ 1, 1, 0x0006, 1, 1, 0x0006 ],
[ 0, 1, 0x0008, 1, 1, 0x0006 ],
[ 0, 1, 0x0008, 0, 0, 0x0006 ],
[ 1, 1, 0x000a, 1, 1, 0x000a ],
[ 0, 1, 0x000c, 1, 1, 0x000a ]
]
# Instantiate and elaborate the model
model = SingleElementSkidQueue( 16 )
model.vcd_file = dump_vcd
if test_verilog:
model = TranslationTool( model )
model.elaborate()
# Define functions mapping the test vector to ports in model
def tv_in( model, test_vector ):
model.enq.val.value = test_vector[0]
model.enq.msg.value = test_vector[2]
model.deq.rdy.value = test_vector[4]
def tv_out( model, test_vector ):
assert model.enq.rdy.value == test_vector[1]
assert model.deq.val.value == test_vector[3]
if not test_vector[5] == '?':
assert model.deq.msg.value == test_vector[5]
# Run the test
sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
sim.run_test()
def test_memresp_from_bits( dump_vcd ):
# Create parameters
memresp_params = mem_msgs.MemRespParams( 32 )
# Test vectors
resp = memresp_params.mk_resp
r = memresp_params.type_read
w = memresp_params.type_write
test_vectors = [
# bits type len data
[ resp( r, 1, 0x000000ab ), r, 1, 0x000000ab ],
[ resp( r, 2, 0x0000abcd ), r, 2, 0x0000abcd ],
[ resp( r, 3, 0x00abcdef ), r, 3, 0x00abcdef ],
[ resp( r, 0, 0xabcdef01 ), r, 0, 0xabcdef01 ],
[ resp( w, 0, 0x00000000 ), w, 0, 0x00000000 ],
]
# Instantiate and elaborate the model
model = mem_msgs.MemRespFromBits( memresp_params )
model.vcd_file = dump_vcd
model.elaborate()
# Define functions mapping the test vector to ports in model
def tv_in( model, test_vector ):
model.bits.value = test_vector[0]
def tv_out( model, test_vector ):
assert model.type_.value == test_vector[1]
assert model.len_.value == test_vector[2]
assert model.data.value == test_vector[3]
# Run the test
sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
sim.run_test()
def test_GtComparator( test_verilog, dump_vcd ):
# Test vectors
test_vectors = [
# in0 in1 out
[ 0x0000, 0x0000, 0 ],
[ 0x0001, 0x0001, 0 ],
[ 0x0000, 0x0001, 0 ],
[ 0x000a, 0x000a, 0 ],
[ 0x000b, 0x000a, 1 ],
[ 0x000b, 0x000c, 0 ],
[ 0x007f, 0x007f, 0 ],
[ 0x0141, 0x0140, 1 ],
[ 0x0400, 0x0400, 0 ],
[ 0x7fff, 0x7fff, 0 ],
[ 0x8000, 0x7fff, 1 ],
[ 0x8001, 0x8002, 0 ],
[ 0xffff, 0xffff, 0 ],
]
# Instantiate and elaborate the model
model = GtComparator(16)
model.vcd_file = dump_vcd
if test_verilog:
model = TranslationTool( model )
model.elaborate()
# Define functions mapping the test vector to ports in model
def tv_in( model, test_vector ):
model.in0.value = test_vector[0]
model.in1.value = test_vector[1]
def tv_out( model, test_vector ):
if test_vector[2] != '?':
assert model.out.value == test_vector[2]
# Run the test
sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
sim.run_test()
def test_RegEn(dump_vcd, test_verilog):
# Test vectors
test_vectors = [
# in en out
[0x0a0a, 0, '?'],
[0x0b0b, 1, '?'],
[0x0c0c, 0, 0x0b0b],
[0x0d0d, 1, 0x0b0b],
[0x0d0d, 0, 0x0d0d],
[0x0d0d, 1, 0x0d0d],
[0x0e0e, 1, 0x0d0d],
[0x0e0e, 0, 0x0e0e],
[0x0f0f, 0, 0x0e0e],
[0x0e0e, 0, 0x0e0e],
[0x0e0e, 0, 0x0e0e],
]
# Instantiate and elaborate the model
model = RegEn(16)
model.vcd_file = dump_vcd
if test_verilog:
model = TranslationTool(model)
model.elaborate()
# Define functions mapping the test vector to ports in model
def tv_in(model, test_vector):
model.in_.value = test_vector[0]
model.en.value = test_vector[1]
def tv_out(model, test_vector):
if test_vector[2] != '?':
assert model.out.value == test_vector[2]
# Run the test
sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
sim.run_test()
def test_regfile_2R1W( dump_vcd, test_verilog ):
# Test vectors
test_vectors = [
# rd_addr0 rd_data0 rd_addr0 rd_data0 wr_en wr_addr wr_data
[ 0, 0x0000, 1, 0x0000, 0, 0, 0x0000 ],
[ 3, 0x0000, 4, 0x0000, 1, 4, 0x0005 ],
[ 3, 0x0000, 4, 0x0005, 1, 2, 0x0006 ],
[ 4, 0x0005, 2, 0x0006, 0, 3, 0x0007 ],
[ 4, 0x0005, 4, 0x0005, 0, 7, 0x0090 ],
[ 4, 0x0005, 7, 0x0000, 0, 7, 0x0090 ],
[ 4, 0x0005, 7, 0x0000, 1, 7, 0x0090 ],
[ 4, 0x0005, 7, 0x0090, 1, 7, 0x0090 ],
]
# Instantiate and elaborate the model
model = RegisterFile( dtype=16, nregs=8, rd_ports=2 )
model.vcd_file = dump_vcd
if test_verilog:
model = TranslationTool( model )
model.elaborate()
# Define functions mapping the test vector to ports in model
def tv_in( model, test_vector ):
model.rd_addr[0].value = test_vector[0]
model.rd_addr[1].value = test_vector[2]
model.wr_en.value = test_vector[4]
model.wr_addr.value = test_vector[5]
model.wr_data.value = test_vector[6]
def tv_out( model, test_vector ):
assert model.rd_data[0].value == test_vector[1]
assert model.rd_data[1].value == test_vector[3]
# Run the test
sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
sim.run_test()
def test_MergerPRTL( test_verilog, dump_vcd ):
test_vectors = [
# in0 in1 in2 in3 in4 in5 in6 in7 in8 in9 idx
[ 0x96, 0x42, 0x03, 0x23, 0x89, 0x55, 0x78, 0x06, 0x09, 0x32, 0x2 ],
[ 0x05, 0x77, 0x32, 0x96, 0x45, 0x23, 0x89, 0x09, 0x09, 0x01, 0x9 ],
[ 0x00, 0x00, 0x03, 0x23, 0x89, 0x35, 0x43, 0x06, 0x09, 0x32, 0x0 ],
]
# random.seed(0xdeadbeef)
# test_vectors = []
# for k in xrange( 50 ):
# inputs = []
# min_value = 0x96
# min_idx = 0
# for i in xrange( 10 ):
# input_value = random.randint( 0, 0x96 )
# if ( input_value < min_value ):
# min_value = input_value
# min_idx = i
# inputs.append( input_value )
# inputs.append( min_idx )
# test_vectors.extend( inputs )
model = MergerPRTL( 10, 8 )
model.vcd_file = dump_vcd
if test_verilog:
model = TranslationTool( model )
model.elaborate()
def tv_in( model, test_vector ):
for i in xrange( 10 ):
model.in_[i].value = test_vector[i]
def tv_out( model, test_vector ):
if test_vector[10] != '?':
assert model.out.value == test_vector[10]
sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
sim.run_test()
def test_RightLogicalShifter( test_verilog, dump_vcd ):
# Test vectors
test_vectors = [
# in shamnt out
[ 0b100000, 1, 0b010000 ],
[ 0b000000, 0, 0b000000 ],
[ 0b100000, 0, 0b100000 ],
[ 0b100000, 2, 0b001000 ],
[ 0b100000, 3, 0b000100 ],
[ 0b100000, 4, 0b000010 ],
[ 0b101010, 1, 0b010101 ],
[ 0b101010, 2, 0b001010 ],
[ 0b111111, 3, 0b000111 ],
[ 0b111111, 6, 0b000000 ],
]
# Instantiate and elaborate the model
model = RightLogicalShifter(6,3)
model.vcd_file = dump_vcd
if test_verilog:
model = TranslationTool( model )
model.elaborate()
# Define functions mapping the test vector to ports in model
def tv_in( model, test_vector ):
model.in_.value = test_vector[0]
model.shamt.value = test_vector[1]
def tv_out( model, test_vector ):
if test_vector[2] != '?':
assert model.out.value == test_vector[2]
# Run the test
sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
sim.run_test()
def test_truncationStep(test_verilog, dump_vcd):
test_vectors = [
# msg_in , lod_in , msg_out , trunc_out
[0b0111111111111111, 0b0000001110, 0b111111, 0x009],
[0b0000001110000000, 0b0000001001, 0b111001, 0x004],
[0b0000001110010000, 0b0000001001, 0b111001, 0x004],
#[ 0b0111111111111111, 0b0000001110, 0b111111, 0x009 ],
#[ 0b0000001110000000, 0b0000000111, 0b110000, 0x001 ],
# [ 0b0000010000000000, 0b0000001010, 0b000000, 0x004 ],
# [ 0b0000000000000000, 0b0000010000, 0b000000, 0x00a ],
# [ 0b0000000000001000, 0b0000000111, 0b000100, 0x001 ],
# [ 0b0000110000000010, 0b0000001001, 0b000000, 0x003 ],
]
# Instantiate and elaborate the model
model = truncationStep(16, 6)
model.vcd_file = dump_vcd
if test_verilog:
model = TranslationTool(model)
model.elaborate()
# Define functions mapping the test vector to ports in model
def tv_in(model, test_vector):
model.msg_in.value = test_vector[0]
model.lod_in.value = test_vector[1]
def tv_out(model, test_vector):
assert model.msg_out.value == test_vector[2]
assert model.trunc_out.value == test_vector[3]
def line_trace(s):
return s.model.line_trace()
# Run the test
sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
sim.run_test()
def test_regfile_1R1Wconst0(dump_vcd, test_verilog):
# Test vectors
test_vectors = [
# rd_addr0 rd_data0 wr_en wr_addr wr_data
[0, 0x0000, 0, 0, 0x0000],
[0, 0x0000, 1, 0, 0x0005],
[0, 0x0000, 0, 0, 0x0000],
[1, '?', 0, 1, 0x0000],
[1, '?', 1, 1, 0x0015],
[1, 0x0015, 0, 1, 0x0000],
[1, 0x0015, 0, 1, 0x0000],
]
# Instantiate and elaborate the model
model = RegisterFile(dtype=16, nregs=8, rd_ports=1, const_zero=True)
model.vcd_file = dump_vcd
if test_verilog:
model = TranslationTool(model, verilator_xinit=test_verilog)
model.elaborate()
# Define functions mapping the test vector to ports in model
def tv_in(model, test_vector):
model.rd_addr[0].value = test_vector[0]
model.wr_en.value = test_vector[2]
model.wr_addr.value = test_vector[3]
model.wr_data.value = test_vector[4]
def tv_out(model, test_vector):
if test_vector[1] != '?':
assert model.rd_data[0].value == test_vector[1]
# Run the test
sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
sim.run_test()
def test_ReducerPRTL(test_verilog, dump_vcd):
test_vectors = [
# in0 in1 in2 rst out
[0x00, 0x00, 0x00, 0x1, 0x96],
[0x32, 0x31, 0x30, 0x0, 0x96],
[0x29, 0x28, 0x29, 0x0, 0x94],
[0x27, 0x29, 0x28, 0x0, 0x8a],
[0x25, 0x23, 0x24, 0x0, 0x7f],
[0x30, 0x29, 0x32, 0x0, 0x72],
[0x07, 0x03, 0x03, 0x0, 0x72],
[0x28, 0x26, 0x25, 0x0, 0x4d],
[0x00, 0x00, 0x00, 0x0, 0x4b],
[0x32, 0x32, 0x32, 0x0, 0x26],
[0x30, 0x31, 0x31, 0x0, 0x26],
[0x30, 0x31, 0x31, 0x1, 0x26],
[0x02, 0x01, 0x05, 0x0, 0x96],
[0x30, 0x01, 0x17, 0x0, 0x65],
[0x30, 0x01, 0x17, 0x0, 0x34],
]
model = ReducerPRTL(3, 6, 3, 50)
model.vcd_file = dump_vcd
if test_verilog:
model = TranslationTool(model)
model.elaborate()
def tv_in(model, test_vector):
model.in_[0].value = test_vector[0]
model.in_[1].value = test_vector[1]
model.in_[2].value = test_vector[2]
model.rst.value = test_vector[3]
def tv_out(model, test_vector):
if test_vector[4] != '?':
assert model.out.value == test_vector[4]
sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
sim.run_test()
def run_test_unsign_unit( test_verilog, dump_vcd, nbits, test_vectors ):
# Instantiate and elaborate the model
model = UnsignUnit( nbits )
model.vcd_file = dump_vcd
if test_verilog:
model = TranslationTool( model )
model.elaborate()
# Define functions mapping the test vector to ports in model
def tv_in( model, test_vector ):
model.in_.value = test_vector[0]
def tv_out( model, test_vector ):
if test_vector[1] != '?':
assert model.out.value == test_vector[1]
# Run the test
sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
sim.run_test()
def test_Demux(dump_vcd, test_verilog):
nports = 2
data_nbits = 16
# Define test input and output functions
def tv_in(model, test_vector):
model.sel.value = test_vector[0]
model.in_.value = test_vector[1]
def tv_out(model, test_vector):
assert model.out[0] == test_vector[2]
assert model.out[1] == test_vector[3]
# Select and elaborate the model under test
model = Demux(nports, dtype=data_nbits)
model.vcd_file = dump_vcd
if test_verilog:
model = TranslationTool(model)
model.elaborate()
# Define the test vectors
test_vectors = [
# sel in_ out[0] out[1]
[0b00, 0x3333, 0x0000, 0x0000],
[0b01, 0x1111, 0x1111, 0x0000],
[0b10, 0x2222, 0x0000, 0x2222],
[0b00, 0x1111, 0x0000, 0x0000],
]
# Create the simulator and configure it
sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
# Run the simulator
sim.run_test()
def run_decoder_test(dump_vcd, test_verilog, model, test_vectors):
# Define test input and output functions
def tv_in(model, test_vector):
model.in_.value = test_vector[0]
def tv_out(model, test_vector):
assert model.out == test_vector[1]
# Select and elaborate the model under test
model.vcd_file = dump_vcd
if test_verilog:
model = TranslationTool(model)
model.elaborate()
# Create the simulator and configure it
sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
# Run the simulator
sim.run_test()
def test_basics(dump_vcd):
# Test vectors
test_vectors = [
# -- in -- -- out --
[4, 3, 3, 4],
[9, 6, 6, 9],
[12, 16, 12, 16],
[12, 16, 12, 16],
]
# Instantiate and elaborate the model
model = MinMax()
model.vcd_file = dump_vcd
model.elaborate()
# Function to set the inputs on the model
def tv_in(model, test_vector):
model.in0.value = test_vector[0]
model.in1.value = test_vector[1]
# Function to verify the outputs from the model
def tv_out(model, test_vector):
if test_vector[2] != '?':
assert model.min.value == test_vector[2]
if test_vector[3] != '?':
assert model.max.value == test_vector[3]
# Create and run the test simulation
sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
sim.run_test()
def test_RegRst(dump_vcd, test_verilog, reset):
test_vectors = [
# in out
[0x0a0a, reset],
[0x0b0b, 0x0a0a],
[0x0c0c, 0x0b0b],
[0x0d0d, 0x0c0c],
[0x0d0d, 0x0d0d],
[0x0d0d, 0x0d0d],
[0x0e0e, 0x0d0d],
[0x0e0e, 0x0e0e],
]
# Instantiate and elaborate the model
model = RegRst(16, reset)
model.vcd_file = dump_vcd
print model.vcd_file
if test_verilog:
model = TranslationTool(model)
model.elaborate()
# Define functions mapping the test vector to ports in model
def tv_in(model, test_vector):
model.in_.value = test_vector[0]
def tv_out(model, test_vector):
if test_vector[1] != '?':
assert model.out.value == test_vector[1]
# Run the test
sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
sim.run_test()
def test_ConfigManager(dump_vcd, test_verilog):
addr_nbits = 5
data_nbits = 32
dec_sel_sz = 3
dec_out_sz = 5
# Define test input and output functions
def tv_in(model, test_vector):
model.proc2asla.val.value = test_vector[0]
model.proc2asla.msg[data_nbits:].value = test_vector[1]
model.proc2asla.msg[:data_nbits].value = test_vector[2]
model.is_asla_done.value = test_vector[3]
def tv_out(model, test_vector):
assert model.proc2asla.rdy == test_vector[4]
if test_vector[5] != '?':
assert model.cfg_data == test_vector[5]
assert model.asla_go == test_vector[6]
assert model.cfg_reg_wen[1] == test_vector[7]
assert model.cfg_reg_wen[2] == test_vector[8]
assert model.cfg_reg_wen[3] == test_vector[9]
assert model.cfg_reg_wen[4] == test_vector[10]
# Select and elaborate the model under test
model = ConfigManager(addr_nbits, data_nbits, dec_sel_sz, dec_out_sz)
model.vcd_file = dump_vcd
if test_verilog:
model = TranslationTool(model)
model.elaborate()
# Define the test vectors
test_vectors = [
# Inputs---------------------- Outputs------------------------------------
# p2a p2a p2a is_alsa p2a cfg asla base base base len
# val addr data done rdy data go a_en b_en c_en en
[0, 1, 0x20000000, 0, 1, 0x20000000, 0, 0, 0, 0, 0],
[1, 1, 0x20000000, 0, 1, 0x20000000, 0, 1, 0, 0, 0],
[1, 2, 0x40000000, 0, 1, 0x40000000, 0, 0, 1, 0, 0],
[1, 3, 0x80000000, 0, 1, 0x80000000, 0, 0, 0, 1, 0],
[1, 4, 0x00000064, 0, 1, 0x00000064, 0, 0, 0, 0, 1],
# TODO: this is different from Verilog test, okay?
#[ 1, 0, 0x00000001, 0, 1, 0x00000001, 1, 0, 0, 0, 0 ],
[1, 0, 0x00000001, 0, 1, 0x00000001, 0, 0, 0, 0, 0],
[0, 0, 0x00000001, 0, 0, '?', 1, 0, 0, 0, 0],
[0, 0, 0x00000001, 0, 0, '?', 1, 0, 0, 0, 0],
# TODO: this is different from Verilog test, okay?
#[ 0, 0, 0x00000001, 1, 1, '?', 0, 0, 0, 0, 0 ],
[0, 0, 0x00000001, 1, 0, '?', 1, 0, 0, 0, 0],
[0, 0, 0x00000001, 0, 1, '?', 0, 0, 0, 0, 0],
]
# Create the simulator and configure it
sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
# Run the simulator
sim.run_test()
