def _getCosimulation(self, module, **kwargs_struct):
'''|
| Returns a co-simulation instance of module.
| Uses the _simulator specified by self._simulator.
| Enables traces if self._trace is True
| module - MyHDL function to be simulated
| kwargs_struct - dict of module structural interface assignments: for signals, interfaces and parameters
|________'''
vals = {}
vals['topname'] = module.get_name() + self.top_suffix
vals['modulepath'] = module.c_path # absolute path
hdlsim = self._simulator
if not hdlsim:
raise ValueError("No _simulator specified")
if not self.sim_reg.has_key(hdlsim):
raise ValueError("Simulator {} is not registered".format(hdlsim))
hdl, analyze_cmd, elaborate_cmd, simulate_cmd = self.sim_reg[hdlsim]
# Convert to HDL
if hdl == "verilog":
# Filter parameters from kwargs_struct and supply them to convert
params = {name: kwargs_struct[name] for name in module.get_all_parameters().keys() if name in kwargs_struct.keys()}
module.convert(hdl=hdl, params=params, verbose=False)
traceFile = module.c_path + '/' + module.out_path + '/' + "{topname}_cosim".format(**vals)
if self._trace:
self._enableTracesVerilog("./tb_{topname}.v".format(**vals), traceFile)
mylog.infob("Co-simulating... trace will be generated ({}.vcd)".format(traceFile))
else:
mylog.infob("Co-simulating... trace will NOT be generated".format(traceFile))
# TODO: Proper handling of VHDL (some day)
# elif hdl == "vhdl":
# toVHDL(module, **kwargs_struct)
# Analyze HDL
os.system(analyze_cmd.format(**vals))
# Elaborate
if elaborate_cmd:
os.system(elaborate_cmd.format(**vals))
# Copy resets and clocks from the structural interface to flat the interface
kwargs_flat = {}
kwargs_flat.update({name : kwargs_struct[name] for name in module.get_all_resets().keys()})
kwargs_flat.update({name : kwargs_struct[name] for name in module.get_all_clocks().keys()})
# Flatten structural interfaces and add them to the flat interface
for name in module.get_all_interfaces().iterkeys():
kwargs_flat.update(kwargs_struct[name].get_all_signals())
# Cosimulation
return Cosimulation(simulate_cmd.format(**vals), **kwargs_flat)
def getDut(self, module, **kwargs):
'''|
| Returns a simulation instance of module.
| Uses the simulator specified by self._simulator.
| Enables traces if self._trace is True
| module - MyHDL module (function 'gen') to be simulated
| kwargs - dict of module interface assignments: for signals and parameters
|________'''
if self._simulator=="myhdl":
if not self._trace:
sim_dut = module.gen(**kwargs)
mylog.infob("Simulating... trace will NOT be generated")
else:
traceSignals.name = module.get_name() + self.top_suffix
sim_dut = traceSignals(module.gen, **kwargs)
mylog.infob("Simulating... trace will be generated ({}.vcd)".format(traceSignals.name))
else:
sim_dut = self._getCosimulation(module, **kwargs)
return sim_dut
def getDut(self, module, **kwargs):
'''|
| Returns a simulation instance of module.
| Uses the simulator specified by self._simulator.
| Enables traces if self._trace is True
| module - MyHDL module (function 'gen') to be simulated
| kwargs - dict of module interface assignments: for signals and parameters
|________'''
if self._simulator == "myhdl":
if not self._trace:
sim_dut = module.gen(**kwargs)
mylog.infob("Simulating... trace will NOT be generated")
else:
traceSignals.name = module.get_name() + self.top_suffix
sim_dut = traceSignals(module.gen, **kwargs)
mylog.infob(
"Simulating... trace will be generated ({}.vcd)".format(
traceSignals.name))
else:
sim_dut = self._getCosimulation(module, **kwargs)
return sim_dut
def _getCosimulation(self, module, **kwargs_struct):
'''|
| Returns a co-simulation instance of module.
| Uses the _simulator specified by self._simulator.
| Enables traces if self._trace is True
| module - MyHDL function to be simulated
| kwargs_struct - dict of module structural interface assignments: for signals, interfaces and parameters
|________'''
vals = {}
vals['topname'] = module.get_name() + self.top_suffix
vals['modulepath'] = module.c_path # absolute path
hdlsim = self._simulator
if not hdlsim:
raise ValueError("No _simulator specified")
if not self.sim_reg.has_key(hdlsim):
raise ValueError("Simulator {} is not registered".format(hdlsim))
hdl, analyze_cmd, elaborate_cmd, simulate_cmd = self.sim_reg[hdlsim]
# Convert to HDL
if hdl == "verilog":
# Filter parameters from kwargs_struct and supply them to convert
params = {
name: kwargs_struct[name]
for name in module.get_all_parameters().keys()
if name in kwargs_struct.keys()
}
module.convert(hdl=hdl, params=params, verbose=False)
traceFile = module.c_path + '/' + module.out_path + '/' + "{topname}_cosim".format(
**vals)
if self._trace:
self._enableTracesVerilog("./tb_{topname}.v".format(**vals),
traceFile)
mylog.infob(
"Co-simulating... trace will be generated ({}.vcd)".format(
traceFile))
else:
mylog.infob(
"Co-simulating... trace will NOT be generated".format(
traceFile))
# TODO: Proper handling of VHDL (some day)
# elif hdl == "vhdl":
# toVHDL(module, **kwargs_struct)
# Analyze HDL
os.system(analyze_cmd.format(**vals))
# Elaborate
if elaborate_cmd:
os.system(elaborate_cmd.format(**vals))
# Copy resets and clocks from the structural interface to flat the interface
kwargs_flat = {}
kwargs_flat.update({
name: kwargs_struct[name]
for name in module.get_all_resets().keys()
})
kwargs_flat.update({
name: kwargs_struct[name]
for name in module.get_all_clocks().keys()
})
# Flatten structural interfaces and add them to the flat interface
for name in module.get_all_interfaces().iterkeys():
kwargs_flat.update(kwargs_struct[name].get_all_signals())
# Cosimulation
return Cosimulation(simulate_cmd.format(**vals), **kwargs_flat)
