def __init__(self):
# call base class constructor
Testable.__init__(self)
self.test_path = os.path.dirname(__file__)
self.cond_mode = []
self.stim_mode = []
self.cond_inc_in = []
self.stim_inc_in = []
self.cond_LEDs = []
self.res_LEDs = []
self.cond_rdy_out = []
self.res_rdy_out = []
self.cond_sim_end = {}
self.tst_data = { "cond_mode":self.cond_mode,\
"stim_mode":self.stim_mode,\
"cond_inc_in":self.cond_inc_in,\
"stim_inc_in":self.stim_inc_in,\
"cond_LEDs":self.cond_LEDs,\
"res_LEDs":self.res_LEDs,\
"cond_rdy_out":self.cond_rdy_out,\
"res_rdy_out":self.res_rdy_out,\
"cond_sim_end": self.cond_sim_end }
self.ref_LEDs = []
self.ref_rdy_out = []
self.ref_data = { "LEDs":(self.ref_LEDs, self.res_LEDs),\
"rdy_out":(self.ref_rdy_out, self.res_rdy_out) }
def __init__(self):
# call base class constructor
Testable.__init__(self)
self.test_path = os.path.dirname(__file__)
self.cond_sbus_wa_wd = []
self.stim_sbus_wa_wd = []
self.cond_sbus_raddr = []
self.stim_sbus_raddr = []
self.cond_sbus_rdata = []
self.res_sbus_rdata = []
self.cond_sim_end = {}
self.tst_data = { "cond_sbus_wa_wd":self.cond_sbus_wa_wd,\
"stim_sbus_wa_wd":self.stim_sbus_wa_wd,\
"cond_sbus_raddr":self.cond_sbus_raddr,\
"stim_sbus_raddr":self.stim_sbus_raddr,\
"cond_sbus_rdata":self.cond_sbus_rdata,\
"res_sbus_rdata":self.res_sbus_rdata,\
"cond_sim_end": self.cond_sim_end }
self.ref_sbus_rdata = []
self.ref_data = { "sbus_rdata":(self.ref_sbus_rdata, self.res_sbus_rdata) }
def __init__(self):
# call base class constructor
Testable.__init__(self)
self.test_path = os.path.dirname(__file__)
self.cond_sbus_wa_wd = []
self.stim_sbus_wa_wd = []
self.cond_sbus_raddr = []
self.stim_sbus_raddr = []
self.cond_sbus_rdata = []
self.res_sbus_rdata = []
self.cond_sim_end = {}
self.tst_data = { "cond_sbus_wa_wd":self.cond_sbus_wa_wd,\
"stim_sbus_wa_wd":self.stim_sbus_wa_wd,\
"cond_sbus_raddr":self.cond_sbus_raddr,\
"stim_sbus_raddr":self.stim_sbus_raddr,\
"cond_sbus_rdata":self.cond_sbus_rdata,\
"res_sbus_rdata":self.res_sbus_rdata,\
"cond_sim_end": self.cond_sim_end }
self.ref_sbus_rdata = []
self.ref_data = {
"sbus_rdata": (self.ref_sbus_rdata, self.res_sbus_rdata)
}
def __init__(self):
# call base class constructor
Testable.__init__(self)
self.test_path = os.path.dirname(__file__)
self.cond_mode = []
self.stim_mode = []
self.cond_inc_in = []
self.stim_inc_in = []
self.cond_LEDs = []
self.res_LEDs = []
self.cond_rdy_out = []
self.res_rdy_out = []
self.cond_sim_end = {}
self.tst_data = { "cond_mode":self.cond_mode,\
"stim_mode":self.stim_mode,\
"cond_inc_in":self.cond_inc_in,\
"stim_inc_in":self.stim_inc_in,\
"cond_LEDs":self.cond_LEDs,\
"res_LEDs":self.res_LEDs,\
"cond_rdy_out":self.cond_rdy_out,\
"res_rdy_out":self.res_rdy_out,\
"cond_sim_end": self.cond_sim_end }
self.ref_LEDs = []
self.ref_rdy_out = []
self.ref_data = { "LEDs":(self.ref_LEDs, self.res_LEDs),\
"rdy_out":(self.ref_rdy_out, self.res_rdy_out) }
def __init__(self):
# call base class constructor
Testable.__init__(self)
self.test_path = os.path.dirname(__file__)
self.cond_mode = []
self.stim_mode = []
self.cond_inc_out = []
self.res_inc_out = []
self.cond_rdy_en = []
self.res_rdy_en = []
self.cond_rdy_buff = []
self.res_rdy_buff = []
self.cond_sim_end = {}
self.tst_data = { "cond_mode":self.cond_mode,\
"stim_mode":self.stim_mode,\
"cond_inc_out":self.cond_inc_out,\
"res_inc_out":self.res_inc_out,\
"cond_rdy_en":self.cond_rdy_en,\
"res_rdy_en":self.res_rdy_en,\
"cond_rdy_buff":self.cond_rdy_buff,\
"res_rdy_buff":self.res_rdy_buff,\
"cond_sim_end": self.cond_sim_end }
self.ref_inc_out = []
self.ref_rdy_en = []
self.ref_rdy_buff = []
self.ref_data = { "inc_out":(self.ref_inc_out, self.res_inc_out),\
"rdy_en":(self.ref_rdy_en, self.res_rdy_en),\
"rdy_buff":(self.ref_rdy_buff, self.res_rdy_buff) }
def __init__(self):
# call base class constructor
Testable.__init__(self)
self.test_path = os.path.dirname(__file__)
self.cond_mode = []
self.stim_mode = []
self.cond_inc_out = []
self.res_inc_out = []
self.cond_rdy_en = []
self.res_rdy_en = []
self.cond_rdy_buff = []
self.res_rdy_buff = []
self.cond_sim_end = {}
self.tst_data = { "cond_mode":self.cond_mode,\
"stim_mode":self.stim_mode,\
"cond_inc_out":self.cond_inc_out,\
"res_inc_out":self.res_inc_out,\
"cond_rdy_en":self.cond_rdy_en,\
"res_rdy_en":self.res_rdy_en,\
"cond_rdy_buff":self.cond_rdy_buff,\
"res_rdy_buff":self.res_rdy_buff,\
"cond_sim_end": self.cond_sim_end }
self.ref_inc_out = []
self.ref_rdy_en = []
self.ref_rdy_buff = []
self.ref_data = { "inc_out":(self.ref_inc_out, self.res_inc_out),\
"rdy_en":(self.ref_rdy_en, self.res_rdy_en),\
"rdy_buff":(self.ref_rdy_buff, self.res_rdy_buff) }
def __init__(self):
# call base class constructor
Testable.__init__(self)
self.test_path = os.path.dirname(__file__)
self.cond_rx16 = []
self.stim_rx16 = []
self.cond_tx16 = []
self.res_tx16 = []
self.cond_rx32 = []
self.stim_rx32 = []
self.cond_tx32 = []
self.res_tx32 = []
self.cond_rx64 = []
self.stim_rx64 = []
self.cond_tx64 = []
self.res_tx64 = []
self.cond_ipg_rx16 = []
self.res_ipg_rx16 = []
self.cond_ipg_tx16 = []
self.res_ipg_tx16 = []
self.cond_sim_end = {}
self.tst_data = { "cond_rx16":self.cond_rx16,\
"stim_rx16":self.stim_rx16,\
"cond_tx16":self.cond_tx16,\
"res_tx16":self.res_tx16,\
"cond_rx32":self.cond_rx32,\
"stim_rx32":self.stim_rx32,\
"cond_tx32":self.cond_tx32,\
"res_tx32":self.res_tx32,\
"cond_rx64":self.cond_rx64,\
"stim_rx64":self.stim_rx64,\
"cond_tx64":self.cond_tx64,\
"res_tx64":self.res_tx64,\
"cond_ipg_rx16":self.cond_ipg_rx16,\
"res_ipg_rx16":self.res_ipg_rx16,\
"cond_ipg_tx16":self.cond_ipg_tx16,\
"res_ipg_tx16":self.res_ipg_tx16,\
"cond_sim_end": self.cond_sim_end }
self.ref_tx16 = []
self.ref_tx32 = []
self.ref_tx64 = []
self.ref_ipg_rx16 = []
self.ref_ipg_tx16 = []
self.ref_data = { "tx16":(self.ref_tx16, self.res_tx16),\
"tx32":(self.ref_tx32, self.res_tx32),\
"tx64":(self.ref_tx64, self.res_tx64),\
"ipg_rx16":(self.ref_ipg_rx16, self.res_ipg_rx16),\
"ipg_tx16":(self.ref_ipg_tx16, self.res_ipg_tx16) }
def __init__(self):
# call base class constructor
Testable.__init__(self)
self.test_path = os.path.dirname(__file__)
self.cond_rx16 = []
self.stim_rx16 = []
self.cond_tx16 = []
self.res_tx16 = []
self.cond_rx32 = []
self.stim_rx32 = []
self.cond_tx32 = []
self.res_tx32 = []
self.cond_rx64 = []
self.stim_rx64 = []
self.cond_tx64 = []
self.res_tx64 = []
self.cond_ipg_rx16 = []
self.res_ipg_rx16 = []
self.cond_ipg_tx16 = []
self.res_ipg_tx16 = []
self.cond_sim_end = {}
self.tst_data = { "cond_rx16":self.cond_rx16,\
"stim_rx16":self.stim_rx16,\
"cond_tx16":self.cond_tx16,\
"res_tx16":self.res_tx16,\
"cond_rx32":self.cond_rx32,\
"stim_rx32":self.stim_rx32,\
"cond_tx32":self.cond_tx32,\
"res_tx32":self.res_tx32,\
"cond_rx64":self.cond_rx64,\
"stim_rx64":self.stim_rx64,\
"cond_tx64":self.cond_tx64,\
"res_tx64":self.res_tx64,\
"cond_ipg_rx16":self.cond_ipg_rx16,\
"res_ipg_rx16":self.res_ipg_rx16,\
"cond_ipg_tx16":self.cond_ipg_tx16,\
"res_ipg_tx16":self.res_ipg_tx16,\
"cond_sim_end": self.cond_sim_end }
self.ref_tx16 = []
self.ref_tx32 = []
self.ref_tx64 = []
self.ref_ipg_rx16 = []
self.ref_ipg_tx16 = []
self.ref_data = { "tx16":(self.ref_tx16, self.res_tx16),\
"tx32":(self.ref_tx32, self.res_tx32),\
"tx64":(self.ref_tx64, self.res_tx64),\
"ipg_rx16":(self.ref_ipg_rx16, self.res_ipg_rx16),\
"ipg_tx16":(self.ref_ipg_tx16, self.res_ipg_tx16) }
def __init__(self):
# call base class constructor
Testable.__init__(self)
self.test_path = os.path.dirname(__file__)
self.cond_tx = []
self.res_tx = []
self.cond_sim_end = {}
self.tst_data = { "cond_tx":self.cond_tx,\
"res_tx":self.res_tx,\
"cond_sim_end": self.cond_sim_end }
self.ref_tx = []
self.ref_data = {"tx": (self.ref_tx, self.res_tx)}
def __init__(self):
# call base class constructor
Testable.__init__(self)
self.test_path = os.path.dirname(__file__)
self.cond_tx = []
self.res_tx = []
self.cond_sim_end = {}
self.tst_data = { "cond_tx":self.cond_tx,\
"res_tx":self.res_tx,\
"cond_sim_end": self.cond_sim_end }
self.ref_tx = []
self.ref_data = { "tx":(self.ref_tx, self.res_tx) }
def __init__(self):
# call base class constructor
Testable.__init__(self)
self.test_path = os.path.dirname(__file__)
self.cond_mode_1 = []
self.stim_mode_1 = []
self.cond_mode_2 = []
self.stim_mode_2 = []
self.cond_LEDs = []
self.res_LEDs = []
self.cond_LED_rdy_en = []
self.res_LED_rdy_en = []
self.cond_LED_rdy_buff = []
self.res_LED_rdy_buff = []
self.cond_LED_rdy_out = []
self.res_LED_rdy_out = []
self.cond_sim_end = {}
self.tst_data = { "cond_mode_1":self.cond_mode_1,\
"stim_mode_1":self.stim_mode_1,\
"cond_mode_2":self.cond_mode_2,\
"stim_mode_2":self.stim_mode_2,\
"cond_LEDs":self.cond_LEDs,\
"res_LEDs":self.res_LEDs,\
"cond_LED_rdy_en":self.cond_LED_rdy_en,\
"res_LED_rdy_en":self.res_LED_rdy_en,\
"cond_LED_rdy_buff":self.cond_LED_rdy_buff,\
"res_LED_rdy_buff":self.res_LED_rdy_buff,\
"cond_LED_rdy_out":self.cond_LED_rdy_out,\
"res_LED_rdy_out":self.res_LED_rdy_out,\
"cond_sim_end": self.cond_sim_end }
self.ref_LEDs = []
self.ref_LED_rdy_en = []
self.ref_LED_rdy_buff = []
self.ref_LED_rdy_out = []
self.ref_data = { "LEDs":(self.ref_LEDs, self.res_LEDs),\
"LED_rdy_en":(self.ref_LED_rdy_en, self.res_LED_rdy_en),\
"LED_rdy_buff":(self.ref_LED_rdy_buff, self.res_LED_rdy_buff),\
"LED_rdy_out":(self.ref_LED_rdy_out, self.res_LED_rdy_out) }
def __init__(self):
# call base class constructor
Testable.__init__(self)
self.test_path = os.path.dirname(__file__)
self.cond_rx_port_flds = []
self.stim_rx_port_flds = []
self.cond_tx_port_flds = []
self.res_tx_port_flds = []
self.cond_sim_end = {}
self.tst_data = { "cond_rx_port_flds":self.cond_rx_port_flds,\
"stim_rx_port_flds":self.stim_rx_port_flds,\
"cond_tx_port_flds":self.cond_tx_port_flds,\
"res_tx_port_flds":self.res_tx_port_flds,\
"cond_sim_end": self.cond_sim_end }
self.ref_tx_port_flds = []
self.ref_data = {
"tx_port_flds": (self.ref_tx_port_flds, self.res_tx_port_flds)
}
def __init__(self):
# call base class constructor
Testable.__init__(self)
self.test_path = os.path.dirname(__file__)
self.cond_rx_width = []
self.stim_rx_width = []
self.cond_tx_width = []
self.res_tx_width = []
self.cond_rx_width1 = []
self.stim_rx_width1 = []
self.cond_tx_width1 = []
self.res_tx_width1 = []
self.cond_rx_fields = []
self.stim_rx_fields = []
self.cond_tx_fields = []
self.res_tx_fields = []
self.cond_rx_width_buf = []
self.stim_rx_width_buf = []
self.cond_tx_width_buf = []
self.res_tx_width_buf = []
self.cond_rx_width1_buf = []
self.stim_rx_width1_buf = []
self.cond_tx_width1_buf = []
self.res_tx_width1_buf = []
self.cond_rx_fields_buf = []
self.stim_rx_fields_buf = []
self.cond_tx_fields_buf = []
self.res_tx_fields_buf = []
self.cond_rx_push = []
self.stim_rx_push = []
self.cond_rx_terminate = []
self.stim_rx_terminate = []
self.cond_tx_terminate = []
self.res_tx_terminate = []
self.cond_ipg_rx_width = []
self.res_ipg_rx_width = []
self.cond_sim_end = {}
self.tst_data = { "cond_rx_width":self.cond_rx_width,\
"stim_rx_width":self.stim_rx_width,\
"cond_tx_width":self.cond_tx_width,\
"res_tx_width":self.res_tx_width,\
"cond_rx_width1":self.cond_rx_width1,\
"stim_rx_width1":self.stim_rx_width1,\
"cond_tx_width1":self.cond_tx_width1,\
"res_tx_width1":self.res_tx_width1,\
"cond_rx_fields":self.cond_rx_fields,\
"stim_rx_fields":self.stim_rx_fields,\
"cond_tx_fields":self.cond_tx_fields,\
"res_tx_fields":self.res_tx_fields,\
"cond_rx_width_buf":self.cond_rx_width_buf,\
"stim_rx_width_buf":self.stim_rx_width_buf,\
"cond_tx_width_buf":self.cond_tx_width_buf,\
"res_tx_width_buf":self.res_tx_width_buf,\
"cond_rx_width1_buf":self.cond_rx_width1_buf,\
"stim_rx_width1_buf":self.stim_rx_width1_buf,\
"cond_tx_width1_buf":self.cond_tx_width1_buf,\
"res_tx_width1_buf":self.res_tx_width1_buf,\
"cond_rx_fields_buf":self.cond_rx_fields_buf,\
"stim_rx_fields_buf":self.stim_rx_fields_buf,\
"cond_tx_fields_buf":self.cond_tx_fields_buf,\
"res_tx_fields_buf":self.res_tx_fields_buf,\
"cond_rx_push":self.cond_rx_push,\
"stim_rx_push":self.stim_rx_push,\
"cond_rx_terminate":self.cond_rx_terminate,\
"stim_rx_terminate":self.stim_rx_terminate,\
"cond_tx_terminate":self.cond_tx_terminate,\
"res_tx_terminate":self.res_tx_terminate,\
"cond_ipg_rx_width":self.cond_ipg_rx_width,\
"res_ipg_rx_width":self.res_ipg_rx_width,\
"cond_sim_end": self.cond_sim_end }
self.ref_tx_width = []
self.ref_tx_width1 = []
self.ref_tx_fields = []
self.ref_tx_width_buf = []
self.ref_tx_width1_buf = []
self.ref_tx_fields_buf = []
self.ref_tx_terminate = []
self.ref_ipg_rx_width = []
self.ref_data = { "tx_width":(self.ref_tx_width, self.res_tx_width),\
"tx_width1":(self.ref_tx_width1, self.res_tx_width1),\
"tx_fields":(self.ref_tx_fields, self.res_tx_fields),\
"tx_width_buf":(self.ref_tx_width_buf, self.res_tx_width_buf),\
"tx_width1_buf":(self.ref_tx_width1_buf, self.res_tx_width1_buf),\
"tx_fields_buf":(self.ref_tx_fields_buf, self.res_tx_fields_buf),\
"tx_terminate":(self.ref_tx_terminate, self.res_tx_terminate),\
"ipg_rx_width":(self.ref_ipg_rx_width, self.res_ipg_rx_width) }
def __init__(self):
# call base class constructor
Testable.__init__(self)
self.test_path = os.path.dirname(__file__)
self.cond_rx_width = []
self.stim_rx_width = []
self.cond_tx_width = []
self.res_tx_width = []
self.cond_rx_width1 = []
self.stim_rx_width1 = []
self.cond_tx_width1 = []
self.res_tx_width1 = []
self.cond_rx_fields = []
self.stim_rx_fields = []
self.cond_tx_fields = []
self.res_tx_fields = []
self.cond_rx_width_buf = []
self.stim_rx_width_buf = []
self.cond_tx_width_buf = []
self.res_tx_width_buf = []
self.cond_rx_width1_buf = []
self.stim_rx_width1_buf = []
self.cond_tx_width1_buf = []
self.res_tx_width1_buf = []
self.cond_rx_fields_buf = []
self.stim_rx_fields_buf = []
self.cond_tx_fields_buf = []
self.res_tx_fields_buf = []
self.cond_rx_push = []
self.stim_rx_push = []
self.cond_rx_terminate = []
self.stim_rx_terminate = []
self.cond_tx_terminate = []
self.res_tx_terminate = []
self.cond_ipg_rx_width = []
self.res_ipg_rx_width = []
self.cond_sim_end = {}
self.tst_data = { "cond_rx_width":self.cond_rx_width,\
"stim_rx_width":self.stim_rx_width,\
"cond_tx_width":self.cond_tx_width,\
"res_tx_width":self.res_tx_width,\
"cond_rx_width1":self.cond_rx_width1,\
"stim_rx_width1":self.stim_rx_width1,\
"cond_tx_width1":self.cond_tx_width1,\
"res_tx_width1":self.res_tx_width1,\
"cond_rx_fields":self.cond_rx_fields,\
"stim_rx_fields":self.stim_rx_fields,\
"cond_tx_fields":self.cond_tx_fields,\
"res_tx_fields":self.res_tx_fields,\
"cond_rx_width_buf":self.cond_rx_width_buf,\
"stim_rx_width_buf":self.stim_rx_width_buf,\
"cond_tx_width_buf":self.cond_tx_width_buf,\
"res_tx_width_buf":self.res_tx_width_buf,\
"cond_rx_width1_buf":self.cond_rx_width1_buf,\
"stim_rx_width1_buf":self.stim_rx_width1_buf,\
"cond_tx_width1_buf":self.cond_tx_width1_buf,\
"res_tx_width1_buf":self.res_tx_width1_buf,\
"cond_rx_fields_buf":self.cond_rx_fields_buf,\
"stim_rx_fields_buf":self.stim_rx_fields_buf,\
"cond_tx_fields_buf":self.cond_tx_fields_buf,\
"res_tx_fields_buf":self.res_tx_fields_buf,\
"cond_rx_push":self.cond_rx_push,\
"stim_rx_push":self.stim_rx_push,\
"cond_rx_terminate":self.cond_rx_terminate,\
"stim_rx_terminate":self.stim_rx_terminate,\
"cond_tx_terminate":self.cond_tx_terminate,\
"res_tx_terminate":self.res_tx_terminate,\
"cond_ipg_rx_width":self.cond_ipg_rx_width,\
"res_ipg_rx_width":self.res_ipg_rx_width,\
"cond_sim_end": self.cond_sim_end }
self.ref_tx_width = []
self.ref_tx_width1 = []
self.ref_tx_fields = []
self.ref_tx_width_buf = []
self.ref_tx_width1_buf = []
self.ref_tx_fields_buf = []
self.ref_tx_terminate = []
self.ref_ipg_rx_width = []
self.ref_data = { "tx_width":(self.ref_tx_width, self.res_tx_width),\
"tx_width1":(self.ref_tx_width1, self.res_tx_width1),\
"tx_fields":(self.ref_tx_fields, self.res_tx_fields),\
"tx_width_buf":(self.ref_tx_width_buf, self.res_tx_width_buf),\
"tx_width1_buf":(self.ref_tx_width1_buf, self.res_tx_width1_buf),\
"tx_fields_buf":(self.ref_tx_fields_buf, self.res_tx_fields_buf),\
"tx_terminate":(self.ref_tx_terminate, self.res_tx_terminate),\
"ipg_rx_width":(self.ref_ipg_rx_width, self.res_ipg_rx_width) }
