def test_cmp(self):
reg_src = instructions.RegSrc(registers.r4)
reg_dst = instructions.RegDst(registers.r5)
cp = instructions.Cmp(reg_src, reg_dst)
self.assertSequenceEqual([cp, reg_src, reg_dst], list(cp.non_leaves))
def test_add_regs(self):
mv = instructions.Addw(instructions.RegSrc(registers.r4),
instructions.RegDst(registers.r5))
self.assertEqual([registers.r4, registers.r5], mv.used_registers)
self.assertEqual([registers.r5], mv.defined_registers)
def test_cmp(self):
cp = instructions.Cmp(instructions.RegSrc(registers.r4),
instructions.RegDst(registers.r5))
self.assertEqual([registers.r4, registers.r5], cp.used_registers)
self.assertEqual([], cp.defined_registers)
def test_mov_reg_mem(self):
mv = instructions.Mov(instructions.RegSrc(registers.r4),
instructions.MemDst(10, registers.r5))
self.assertEqual([registers.r4, registers.r5], mv.used_registers)
self.assertEqual([], mv.defined_registers)
def test_add(self):
add = instructions.Addw(instructions.RegSrc(registers.r2),
instructions.RegDst(registers.r3))
self.assertEqual('add.w R2, R3', str(add))
