def __init__(self, name, mapping, parent=None):
portlist = dict([('OUT', gate.OUT), ('I0', gate.IN), ('I1', gate.IN),
('I2', gate.IN)])
gate.module.__init__(self,
name=name,
portlist=portlist,
mapping=mapping,
parent=parent)
for i in ('n0', 'n1', 'n2'):
self.netlist[i] = net.net(i, parent=self)
# Add depln mode pullups
self.netlist['n0'].pullup_str = 100
self.port['OUT'].netconn.pullup_str = 100
self.gatelist.extend([
UNMOS("NMOS_0_u", [
self.netlist['n0'], self.netlist['n1'], self.port['I0'].netconn
], self),
UNMOS("NMOS_1_u", [
self.netlist['n1'], self.netlist['n2'], self.port['I1'].netconn
], self),
UNMOS("NMOS_2_u", [
self.netlist['n2'], self.netlist['vss'],
self.port['I2'].netconn
], self),
UNMOS("NMOS_3_u", [
self.port['OUT'].netconn, self.netlist['vss'],
self.netlist['n0']
], self),
])
def __init__(self, options):
testbench.__init__(self,options)
self.netlist.update( gate.wire([ 'in0', 'in1', 'out', 'n0']))
self.netlist['out'].pullup_str=1
dut0 = UNMOS( "unmos_0_u", [ self.netlist['n0'], self.netlist['vss'], self.netlist['in0']], self)
dut1 = UNMOS( "unmos_1_u", [ self.netlist['out'], self.netlist['n0'], self.netlist['in1']], self)
self.gatelist = [dut0, dut1]
vector_string = '''
PI in0
PI in1
PO out
# ii o
# nn u
# 01 t
# ------
00 H
01 H
10 H
11 L
01 H
10 H
00 H
10 H
11 L
'''
self.events = self.read_flex_string( vector_string)
def __init__(self, name, mapping, parent=None):
portlist = dict([('Q', gate.OUT), ('D', gate.IN), ('RSTB', gate.IN),
('PHI', gate.IN)])
gate.module.__init__(self,
name=name,
portlist=portlist,
mapping=mapping,
parent=parent)
for i in ('phib', 'rst', 'n0'):
self.netlist[i] = net.net(i, parent=self, pullup_str=100)
self.netlist['n1'] = net.net('n1', parent=self, charge_storage=True)
self.netlist['n2'] = net.net('n2', parent=self, charge_storage=True)
self.port['Q'].netconn.pullup_str += 100
self.gatelist.extend([
# Inverters for the clock and reset signals
UNMOS("NMOS_0_u", [
self.netlist['phib'], self.netlist['vss'],
self.port['PHI'].netconn
], self),
UNMOS("NMOS_1_u", [
self.netlist['rst'], self.netlist['vss'],
self.port['RSTB'].netconn
], self),
# 2 half latches
UNMOS(
"NMOS_2_u",
[self.netlist['n0'], self.netlist['vss'], self.netlist['n1']],
self),
UNMOS("NMOS_3_u", [
self.netlist['n1'], self.port['D'].netconn,
self.netlist['phib']
], self),
UNMOS("NMOS_4_u", [
self.port['Q'].netconn, self.netlist['vss'], self.netlist['n2']
], self),
UNMOS("NMOS_5_u", [
self.netlist['n2'], self.netlist['n0'],
self.port['PHI'].netconn
], self),
# Reset first and second latches in opposite directions - must be strong drivers to win contention vs pass gates
UNMOS(
"NMOS_6_u",
[self.netlist['n1'], self.netlist['vss'], self.netlist['rst']],
self),
UNMOS(
"NMOS_7_u",
[self.netlist['n2'], self.netlist['vdd'], self.netlist['rst']],
self),
])
def __init__(self, name, mapping, parent=None):
portlist = dict([('OUT', gate.OUT), ('IN', gate.IN)])
gate.module.__init__(self,
name=name,
portlist=portlist,
mapping=mapping,
parent=parent)
# Add depln mode pullups
self.netlist['n0'] = net.net('n0', pullup_str=100, parent=self)
self.port['OUT'].netconn.pullup_str = 100
self.gatelist.extend([
UNMOS("NMOS_0_u", [
self.port['OUT'].netconn, self.netlist['vss'],
self.netlist['n0']
], self),
UNMOS("NMOS_1_u", [
self.netlist['n0'], self.netlist['vss'],
self.port['IN'].netconn
], self),
])
def __init__(self, name, mapping, parent=None):
portlist = dict([('OUT', gate.OUT), ('I0', gate.IN), ('I1', gate.IN),
('I2', gate.IN)])
gate.module.__init__(self,
name=name,
portlist=portlist,
mapping=mapping,
parent=parent)
# Add depln mode pullups
self.port['OUT'].netconn.pullup_str = 100
self.netlist['n0'] = net.net('n0', parent=self)
self.netlist['n1'] = net.net('n1', parent=self)
self.gatelist.extend([
UNMOS("NMOS_0_u", [
self.port['OUT'].netconn, self.netlist['n0'],
self.port['I0'].netconn
], self),
UNMOS("NMOS_1_u", [
self.port['OUT'].netconn, self.netlist['n1'],
self.port['I1'].netconn
], self),
UNMOS("NMOS_2_u", [
self.netlist['n0'], self.netlist['vss'],
self.port['I1'].netconn
], self),
UNMOS("NMOS_3_u", [
self.netlist['n1'], self.netlist['vss'],
self.port['I0'].netconn
], self),
# This has to be a bidir gate to work
NMOS("NMOS_4_u", [
self.netlist['n1'], self.netlist['n0'], self.port['I2'].netconn
], self),
])
def __init__(self, options):
testbench.__init__(self, options)
self.netlist.update(
gate.wire([
'in0', 'in1', 'in2', 'n0', 'n1', 'n2', 'n2b', 'mx0', 'mx1',
'out', 'out1'
]))
self.netlist['mx0'].charge_storage = True
self.gatelist = [
INV("inv_0_u", [self.netlist['n0'], self.netlist['in0']], self),
INV("inv_1_u", [self.netlist['n1'], self.netlist['in1']], self),
INV("inv_2_u", [self.netlist['n2b'], self.netlist['in2']], self),
BUF("buf_0_u", [self.netlist['n2'], self.netlist['in2']], self),
UNMOS(
"nmos_0_u",
[self.netlist['mx0'], self.netlist['n0'], self.netlist['n2b']],
self),
UNMOS(
"nmos_1_u",
[self.netlist['mx0'], self.netlist['n1'], self.netlist['in2']],
self),
UNMOS(
"nmos_2_u",
[self.netlist['mx1'], self.netlist['n0'], self.netlist['n2b']],
self),
UNMOS(
"nmos_3_u",
[self.netlist['mx1'], self.netlist['n1'], self.netlist['n2']],
self),
INV("inv_3_u", [self.netlist['out'], self.netlist['mx0']], self),
INV("inv_4_u", [self.netlist['out1'], self.netlist['mx1']], self),
]
vector_string = '''
PI in0
PI in1
PI in2
PO out
# o
# iii ou
# nnn ut
# 012 t1
# -------------
000 LL
001 LL
010 LL
011 HH
100 HH
101 LL
110 HH
111 HH
000 LL
001 LL
010 LL
011 HH
'''
self.events = self.read_flex_string(vector_string)
def __init__(self, options):
testbench.__init__(self, options)
self.netlist.update(
gate.wire([
'in0', 'in1', 'in2', 'in3', 'in4', 'in5', 'n0', 'n1', 'n2',
'n3', 'out'
]))
self.netlist['out'].pullup_str = net.DEPL_STR
self.netlist['n0'].pullup_str = net.DEPL_STR
self.netlist['n1'].pullup_str = net.DEPL_STR
self.netlist['n2'].charge_storage = True
self.netlist['n3'].charge_storage = True
self.gatelist = [
NMOS(
"nmos_0_u",
[self.netlist['n0'], self.netlist['vss'], self.netlist['in0']],
self),
NMOS(
"nmos_1_u",
[self.netlist['n1'], self.netlist['vss'], self.netlist['in1']],
self),
NMOS(
"nmos_2_u",
[self.netlist['n2'], self.netlist['vss'], self.netlist['in2']],
self),
NMOS("nmos_3_u",
[self.netlist['n0'], self.netlist['n2'], self.netlist['in3']],
self),
NMOS("nmos_4_u",
[self.netlist['n1'], self.netlist['n2'], self.netlist['in4']],
self),
UNMOS(
"unmos_5_u",
[self.netlist['n3'], self.netlist['n2'], self.netlist['in5']],
self),
NMOS(
"nmos_6_u",
[self.netlist['out'], self.netlist['vss'], self.netlist['n3']],
self),
]
vector_string = '''
PI in0
PI in1
PI in2
PI in3
PI in4
PI in5
PO n2
PO out
# iiiiii o
# nnnnnn n u
# 012345 2 t
# -------------
111111 L H
000000 L H
000100 H H
000001 H L
000000 H L
101010 L L
010101 H L
000110 H L
000101 H L
101000 L L
000001 L H
'''
self.events = self.read_flex_string(vector_string)