Exemplo n.º 1
0
    def testOk(self):
        """Tests that no problems are signaled in case all registers are valid
        and there are no references to nonexistent registers."""
        proc = processor.Processor('test', '0')
        regBank = processor.RegisterBank('RB', 30, 32)
        proc.addRegBank(regBank)
        cpsrBitMask = {'N': (31, 31), 'Z': (30, 30), 'C': (29, 29), 'V': (28, 28), 'I': (7, 7), 'F': (6, 6), 'mode': (0, 4)}
        cpsr = processor.Register('CPSR', 32, cpsrBitMask)
        cpsr.setDefaultValue(0x000000D3)
        proc.addRegister(cpsr)
        regs = processor.AliasRegBank('REGS', 16, 'RB[0-15]')
        proc.addAliasRegBank(regs)
        abi = processor.ABI('REGS[0]', 'REGS[0-3]', 'RB[15]')
        abi.addVarRegsCorrespondence({'REGS[0-15]': (0, 15), 'CPSR': (25, 25)})
        proc.setABI(abi)
        dataProc_imm_shift = isa.MachineCode([('cond', 4), ('zero', 3), ('opcode', 4), ('s', 1), ('rn', 4), ('rd', 4), ('shift_amm', 5), ('shift_op', 2), ('zero', 1), ('rm', 4)])
        dataProc_imm_shift.setVarField('rn', ('REGS', 0))
        dataProc_imm_shift.setVarField('rd', ('RB', 0))
        dataProc_imm_shift.setVarField('rm', ('REGS', 0))
        isaVar = isa.ISA()
        proc.setISA(isaVar)
        opCode = cxx_writer.Code('')
        adc_shift_imm_Instr = isa.Instruction('ADC_si', True)
        adc_shift_imm_Instr.setMachineCode(dataProc_imm_shift, {'opcode': [0, 1, 0, 1]}, 'TODO')
        isaVar.addInstruction(adc_shift_imm_Instr)

        # Call the check functions: They raise exceptions if there is a problem.
        proc.checkAliases()
        proc.checkABI()
        proc.isa.checkRegisters(processor.extractRegInterval, proc.isRegExisting)
Exemplo n.º 2
0
    def testABIReg(self):
        """Tests that an exception is raised in case the ABI refers to
        a non existing register"""
        proc = processor.Processor('test', '0')
        regBank = processor.RegisterBank('RB', 30, 32)
        proc.addRegBank(regBank)
        cpsrBitMask = {
            'N': (31, 31),
            'Z': (30, 30),
            'C': (29, 29),
            'V': (28, 28),
            'I': (7, 7),
            'F': (6, 6),
            'mode': (0, 4)
        }
        cpsr = processor.Register('CPSR', 32, cpsrBitMask)
        cpsr.setDefaultValue(0x000000D3)
        proc.addRegister(cpsr)
        regs = processor.AliasRegBank('REGS', 16, 'RB[0-15]')
        proc.addAliasRegBank(regs)
        PC = processor.AliasRegister('PC', 'REGS[15]')
        proc.addAliasReg(PC)
        abi = processor.ABI('REGS[0]', 'REGS[0-3]', 'RB[15]')
        abi.addVarRegsCorrespondence({
            'REGS[0-15]': (0, 15),
            'UNEXISTING': (25, 25)
        })
        proc.setABI(abi)
        dataProc_imm_shift = isa.MachineCode([('cond', 4), ('zero', 3),
                                              ('opcode', 4), ('s', 1),
                                              ('rn', 4), ('rd', 4),
                                              ('shift_amm', 5),
                                              ('shift_op', 2), ('zero', 1),
                                              ('rm', 4)])
        dataProc_imm_shift.setVarField('rn', ('REGS', 0))
        dataProc_imm_shift.setVarField('rd', ('RB', 0))
        dataProc_imm_shift.setVarField('rm', ('REGS', 0))
        isaVar = isa.ISA()
        proc.setISA(isaVar)
        opCode = cxx_writer.writer_code.Code('')
        adc_shift_imm_Instr = isa.Instruction('ADC_si', True)
        adc_shift_imm_Instr.setMachineCode(dataProc_imm_shift,
                                           {'opcode': [0, 1, 0, 1]}, 'TODO')
        isaVar.addInstruction(adc_shift_imm_Instr)

        # The I call the check functions: they raise exceptions in case
        # there is a problem
        foundError = False
        proc.isa.checkRegisters(processor.extractRegInterval,
                                proc.isRegExisting)
        proc.checkAliases()
        try:
            proc.checkABI()
        except:
            foundError = True
        self.assert_(foundError)