def test_type_eq():
assert equal(UnknownType(), UnknownType())
assert equal(ClockType(), ClockType())
assert equal(uw(10), uw(10))
assert equal(sw(10), sw(10))
assert equal(vec(uw(10), 8), vec(uw(10), 8))
assert equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), True)),
bdl(a=(vec(uw(10), 8), False), b=(uw(10), True)))
def test_write_port_mem_wrong():
mem_ref = n("m", bdl(a=(vec(uw(8), 10), False)))
mw = DefMemWritePort("mw", mem_ref, u(2, w(8)), n("clock", ClockType()))
assert not check(mw)
mem_ref = n("m", uw(9))
mw = DefMemWritePort("mw", mem_ref, n("a", uw(2)), n("clock", ClockType()))
assert not check(mw)
def test_init_register_type_not_match():
r1 = DefInitRegister("r1", uw(8), n("clock", ClockType()), n("r", uw(1)),
s(5, w(8)))
assert not check(r1)
r2 = DefInitRegister("r2", uw(8), n("clock", ClockType()), u(0, w(1)),
s(5, w(8)))
assert not check(r2)
def test_register_basis():
r1 = DefRegister("r1", uw(8), n("clock", ClockType()))
assert check(r1)
serialize_stmt_equal(r1, 'reg r1 : UInt<8>, clock')
r2 = DefRegister("r2", vec(uw(8), 10), n("clock", ClockType()))
assert check(r2)
serialize_stmt_equal(r2, 'reg r2 : UInt<8>[10], clock')
def test_read_port_mem_wrong():
mem_ref = n("m", bdl(a=(vec(uw(8), 10), False)))
mr = DefMemReadPort("mr", mem_ref, u(2, w(8)), n("clock", ClockType()))
assert not check(mr)
mem_ref = n("m", uw(9))
mr = DefMemReadPort("mr", mem_ref, n("a", uw(2)), n("clock", ClockType()))
assert not check(mr)
def test_init_register_reset_wrong():
r1 = DefInitRegister("r1", uw(8), n("clock", ClockType()), n("r", sw(1)),
u(5, w(8)))
assert not check(r1)
r2 = DefInitRegister("r2", sw(8), n("clock", ClockType()), s(0, w(1)),
s(5, w(8)))
assert not check(r2)
def test_write_port_index_wrong():
mem_ref = n("m", vec(uw(8), 10))
mw = DefMemWritePort("mw", mem_ref, s(2, w(8)), n("clock", ClockType()))
assert not check(mw)
mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10))
mw = DefMemWritePort("mw", mem_ref, n("a", vec(uw(1), 10)),
n("clock", ClockType()))
assert not check(mw)
def test_read_port_index_wrong():
mem_ref = n("m", vec(uw(8), 10))
mr = DefMemReadPort("mr", mem_ref, s(2, w(8)), n("clock", ClockType()))
assert not check(mr)
mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10))
mr = DefMemReadPort("mr", mem_ref, n("a", vec(uw(1), 10)),
n("clock", ClockType()))
assert not check(mr)
def test_read_port_basis():
mem_ref = n("m", vec(uw(8), 10))
mr = DefMemReadPort("mr", mem_ref, u(2, w(8)), n("clock", ClockType()))
assert check(mr)
serialize_stmt_equal(mr, 'read mport mr = m[UInt<8>("h2")], clock')
mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10))
mr = DefMemReadPort("mr", mem_ref, n("a", uw(2)), n("clock", ClockType()))
assert check(mr)
serialize_stmt_equal(mr, 'read mport mr = m[a], clock')
def test_write_port_basis():
mem_ref = n("m", vec(uw(8), 10))
mw = DefMemWritePort("mw", mem_ref, u(2, w(8)), n("clock", ClockType()))
assert check(mw)
serialize_stmt_equal(mw, 'write mport mw = m[UInt<8>("h2")], clock')
mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10))
mw = DefMemWritePort("mw", mem_ref, n("a", uw(2)), n("clock", ClockType()))
assert check(mw)
serialize_stmt_equal(mw, 'write mport mw = m[a], clock')
def test_init_register_basis():
r1 = DefInitRegister("r1", uw(8), n("clock", ClockType()), n("r", uw(1)),
u(5, w(8)))
assert check(r1)
serialize_stmt_equal(
r1, 'reg r1 : UInt<8>, clock with :\n'
' reset => (r, UInt<8>("h5"))')
r2 = DefInitRegister("r2", sw(8), n("clock", ClockType()), u(0, w(1)),
s(5, w(8)))
assert check(r2)
serialize_stmt_equal(
r2, 'reg r2 : SInt<8>, clock with :\n'
' reset => (UInt<1>("h0"), SInt<8>("h5"))')
def test_asuint():
basis_tester(asuint_basis_cases)
encounter_error_tester(asuint_type_wrong_cases)
encounter_error_tester(asuint_width_wrong_cases)
serialize_equal(AsUInt(u(20, w(5)), uw(5)), 'asUInt(UInt<5>("h14"))')
serialize_equal(AsUInt(s(-20, w(6)), uw(5)), 'asUInt(SInt<6>("h-14"))')
serialize_equal(AsUInt(n("clock", ClockType()), uw(1)), 'asUInt(clock)')
def convert_expr(mi: ModuleInst):
if mi.module_name not in Context.modules:
from .conv_module import convert_module
convert_module(mi.packed_module)
module = Context.modules[mi.module_name]
name = NameGetter.get(mi.id)
ref = Reference(name, ports_to_bundle_type(module.ports))
stmts = [
DefInstance(name, mi.module_name),
Connect(SubField(ref, 'clock', ClockType()),
Reference('clock', ClockType())),
Connect(SubField(ref, 'reset', UIntType(Width(1))),
Reference('reset', UIntType(Width(1))))
]
Context.expr_obj_id_to_ref[id(mi)] = ref
return stmts, ref
def convert_ports(raw_ports: Dict[str, Union[Input, Output]]):
ports = [InputPort('clock', ClockType()),
InputPort('reset', UIntType(Width(1)))]
for k, v in raw_ports.items():
p = InputPort if v.port_dir == 'input' else OutputPort
ports.append(p(k, convert_type(v.hcl_type)))
return ports
def test_type_neq():
assert not equal(UnknownType(), ClockType())
assert not equal(UnknownType(), uw(10))
assert not equal(UnknownType(), sw(10))
assert not equal(UnknownType(), vec(uw(10), 8))
assert not equal(UnknownType(), vec(sw(10), 8))
assert not equal(UnknownType(),
bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)))
assert not equal(ClockType(), UnknownType())
assert not equal(ClockType(), uw(10))
assert not equal(ClockType(), sw(10))
assert not equal(ClockType(), vec(uw(10), 8))
assert not equal(ClockType(), vec(sw(10), 8))
assert not equal(ClockType(),
bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)))
assert not equal(uw(10), UnknownType())
assert not equal(uw(10), ClockType())
assert not equal(uw(10), uw(8))
assert not equal(uw(10), sw(10))
assert not equal(uw(10), sw(10))
assert not equal(uw(10), vec(uw(10), 8))
assert not equal(uw(10), vec(sw(10), 8))
assert not equal(uw(10),
bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)))
assert not equal(sw(10), UnknownType())
assert not equal(sw(10), ClockType())
assert not equal(sw(10), sw(8))
assert not equal(sw(10), uw(10))
assert not equal(sw(10), uw(10))
assert not equal(sw(10), vec(uw(10), 8))
assert not equal(sw(10), vec(sw(10), 8))
assert not equal(sw(10),
bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)))
assert not equal(vec(uw(10), 8), UnknownType())
assert not equal(vec(uw(10), 8), ClockType())
assert not equal(vec(uw(10), 8), sw(8))
assert not equal(vec(uw(10), 8), uw(10))
assert not equal(vec(uw(10), 8), uw(10))
assert not equal(vec(uw(10), 8), vec(uw(8), 8))
assert not equal(vec(uw(10), 8), vec(uw(10), 9))
assert not equal(vec(uw(10), 8), vec(sw(10), 8))
assert not equal(vec(uw(10), 8),
bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)))
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
UnknownType())
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
ClockType())
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
sw(8))
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
uw(10))
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
uw(10))
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
vec(sw(10), 8))
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
bdl(a=(vec(uw(10), 8), True), b=(uw(10), False)))
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
bdl(a=(vec(uw(10), 2), False), b=(uw(10), False)))
assert not equal(bdl(a=(uw(3), False), b=(uw(10), False)),
bdl(a=(uw(3), False), b=(uw(10), False), c=(sw(2), True)))
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
bdl(b=(uw(10), False), a=(vec(uw(10), 8), False)))
def test_clock_type():
serialize_equal(ClockType(), "Clock")
def clock_gen():
return n(name_gen(), ClockType())