def assig_process_sc_signal(self):
(
c,
cVld,
) = sim_eval_cond(self.io.a.val._eq(self.const_1_3))
if not cVld:
self.io.sc_signal.val_next = (
self.const_0_3,
0,
)
elif c:
self.io.sc_signal.val_next = (
self.const_0_4,
0,
)
else:
(
c,
cVld,
) = sim_eval_cond(self.io.a.val._eq(self.const_2_2))
if not cVld:
self.io.sc_signal.val_next = (
self.const_0_3,
0,
)
elif c:
self.io.sc_signal.val_next = (
self.const_1_2,
0,
)
else:
(
c,
cVld,
) = sim_eval_cond(self.io.a.val._eq(self.const_3_0))
if not cVld:
self.io.sc_signal.val_next = (
self.const_0_3,
0,
)
elif c:
self.io.sc_signal.val_next = (
self.const_3_1,
0,
)
else:
self.io.sc_signal.val_next = (
self.const_4_2,
0,
)
def assig_process_h(self):
(
c,
cVld,
) = sim_eval_cond(self.io.a.val[self.const_2_0]._eq(self.const_1_1))
if not cVld:
self.io.h.val_next = (
self.const_0_3,
0,
)
elif c:
(
c,
cVld,
) = sim_eval_cond(self.io.r.val._eq(self.const_1_1))
if not cVld:
self.io.h.val_next = (
self.const_0_3,
0,
)
elif c:
self.io.h.val_next = (
self.const_0_4,
0,
)
else:
(
c,
cVld,
) = sim_eval_cond(self.io.a.val[self.const_1_0]._eq(
self.const_1_1))
if not cVld:
self.io.h.val_next = (
self.const_0_3,
0,
)
elif c:
self.io.h.val_next = (
self.const_1_2,
0,
)
else:
self.io.h.val_next = (
self.const_2_1,
0,
)
else:
pass
def assig_process_fallingEdgeRam(self):
(
c,
cVld,
) = sim_eval_cond(self.io.clk._onFallingEdge())
if not cVld:
self.io.fallingEdgeRam.val_next = (
self.const_0,
1,
)
self.io.k.val_next = (
self.const_0_0,
1,
)
elif c:
self.io.fallingEdgeRam.val_next = (
self.io.a.val[self.const_1].cast_sign(False),
(self.io.r_1.val, ),
1,
)
self.io.k.val_next = (
self.const_0_1._concat(self.io.fallingEdgeRam.val[
self.io.r_1.val].cast_sign(True)),
1,
)
else:
pass
def assig_process_a_dout(self):
(
c,
cVld,
) = sim_eval_cond(self.io.a_clk._onRisingEdge()
& self.io.a_en.val._eq(self.const_1_0))
if not cVld:
self.io.ram_memory.val_next = (
self.const_0,
1,
)
self.io.a_dout.val_next = (
self.const_0_0,
1,
)
elif c:
(
c,
cVld,
) = sim_eval_cond(self.io.a_we.val._eq(self.const_1_0))
if not cVld:
self.io.ram_memory.val_next = (
self.const_0,
1,
)
elif c:
self.io.ram_memory.val_next = (
self.io.a_din.val,
(self.io.a_addr.val, ),
1,
)
else:
pass
self.io.a_dout.val_next = (
self.io.ram_memory.val[self.io.a_addr.val],
1,
)
else:
pass
def assig_process_j(self):
(
c,
cVld,
) = sim_eval_cond(self.io.clk._onRisingEdge())
if not cVld:
self.io.j.val_next = (
self.const_0_3,
1,
)
elif c:
self.io.j.val_next = (
self.rom[self.io.r_1.val],
1,
)
else:
pass
def assig_process_r_next_1(self):
(
c,
cVld,
) = sim_eval_cond((~(self.io.r.val))._eq(self.const_1_1))
if not cVld:
self.io.r_next.val_next = (
self.const_0_6,
0,
)
elif c:
self.io.r_next.val_next = (
self.io.e.val,
0,
)
else:
self.io.r_next.val_next = (
self.io.r.val,
0,
)
def assig_process_r(self):
(
c,
cVld,
) = sim_eval_cond(self.io.clk._onRisingEdge())
if not cVld:
self.io.r_1.val_next = (
self.const_0_7,
1,
)
self.io.r_0.val_next = (
self.const_0_7,
1,
)
self.io.r.val_next = (
self.const_0_6,
1,
)
elif c:
(
c,
cVld,
) = sim_eval_cond(self.io.rst_n.val._eq(self.const_0_5))
if not cVld:
self.io.r_1.val_next = (
self.const_0_7,
1,
)
self.io.r_0.val_next = (
self.const_0_7,
1,
)
self.io.r.val_next = (
self.const_0_6,
1,
)
elif c:
self.io.r_1.val_next = (
self.const_0_8,
1,
)
self.io.r_0.val_next = (
self.const_0_8,
1,
)
self.io.r.val_next = (
self.const_0_5,
1,
)
else:
self.io.r_1.val_next = (
self.io.r_next_1.val,
1,
)
self.io.r_0.val_next = (
self.io.r_next_0.val,
1,
)
self.io.r.val_next = (
self.io.r_next.val,
1,
)
else:
pass
