def test_output_gpio(self):
"""Simple test to demonstrate ouput bit-banging on CBUS.
You need a CBUS-capable FTDI (FT232R/FT232H/FT230X/FT231X), whose
EEPROM has been configured to support GPIOs on CBUS0 and CBUS3.
Hard-wiring is required to run this test:
* CBUS0 (output) should be connected to CTS (input)
* CBUS3 (output) should be connected to DSR (input)
"""
ftdi = Ftdi()
ftdi.open_from_url(self.url)
# sanity check: device should support CBUS feature
self.assertEqual(ftdi.has_cbus, True)
eeprom = FtdiEeprom()
eeprom.connect(ftdi)
# sanity check: device should have been configured for CBUS GPIOs
self.assertEqual(eeprom.cbus_mask & 0b1001, 0b1001)
# configure CBUS0 and CBUS3 as output
ftdi.set_cbus_direction(0b1001, 0b1001)
# no input pin available
self.assertRaises(FtdiError, ftdi.get_cbus_gpio)
for cycle in range(40):
value = cycle & 0x3
# CBUS0 and CBUS3
cbus = ((value & 0x2) << 2) | value & 0x1
# for now, need a digital/logic analyzer to validate output
ftdi.set_cbus_gpio(cbus)
# CBUS0 is connected to CTS, CBUS3 to DSR
# need to inverse logical level as RS232 uses negative logic
sig = int(not ftdi.get_cts()) | (int(not ftdi.get_dsr()) << 1)
self.assertEqual(value, sig)
# print ("______________")
ft.set_flowctrl('')
ft.purge_buffers()
ft.purge_tx_buffer()
ft.purge_rx_buffer()
ft.set_break(False)
#ft.set_flowctrl()
ft.read_data_bytes(5).tolist()
fifo_wr = []
for i in range(N):
aux = (i + 1) % 256
aux = randint(0, 255)
fifo_wr.append(aux)
print("______________")
print("CTS? {}\tDSR? {}\tRI? {}".format(ft.get_cts(), ft.get_dsr(),
ft.get_ri()))
print("Poll Modem status? {}\tModem Status? {}".format(
ft.poll_modem_status(), ft.modem_status()))
print("______________")
print("\twrite: " + str(ft.write_data(bytes([aux]))), aux)
time.sleep(0.01)
aux = ft.read_data_bytes(5).tolist()
if (len(aux) > 0):
print("\tread = {}".format(aux))
fifo_rd = fifo_rd + aux
else:
print("\t...")
print("\n... Reading more...")
while True: