def test_conf_getter():
clear()
def get_b(var):
return var.path
reg.confdef('a/b', getter=get_b)
assert reg['a/b'] == 'a/b'
def bind(cls):
global gear_reg, sim_reg
gear_reg = {}
sim_reg = {}
reg['sim/config'] = {}
reg['sim/flow'] = []
reg['sim/tasks'] = {}
reg['sim/simulator'] = None
reg['sim/step_timeout'] = 0
reg['sim/dryrun'] = False
reg['sim'].subreg('hook')
reg['sim/hook/cosim_build_before'] = SimEvent()
reg['sim/hook/cosim_build_after'] = SimEvent()
reg['gear/exec_context'] = None
reg['sim/postmortem'] = False
reg['sim/exception'] = None
reg['sim/traceback'] = None
reg.confdef('sim/rand_seed', None)
reg.confdef('sim/clk_freq', 1000)
reg.confdef('results-dir', default=tempfile.mkdtemp())
reg.confdef('sim/extens', default=[])
reg['gear/params/meta/sim_setup'] = None
register_custom_log('sim', cls=SimLog)
# temporary hack for pytest logger reset issue
reg['logger/sim/error'] = 'exception'
reg['logger/sim/print_traceback'] = False
def bind(cls):
conf = cmd_register(['ipgen', 'vivado'],
ipgen,
aliases=['viv'],
derived=True)
reg.confdef('vivado/iplib',
default=os.path.join(CACHE_DIR, 'vivado', 'iplib'))
reg['vivado/ipgen/lock'] = False
conf['parser'].add_argument('--intf', type=str)
conf['parser'].add_argument('--presynth', '-p', action='store_false')
conf['parser'].add_argument('--prjdir', type=str)
def test_conf_setter():
clear()
values = []
def set_b(var, val):
if val is None:
return
values.append(val)
reg.confdef('a/b', setter=set_b)
reg['a/b'] = 1
reg['a/b'] = 2
assert values == [1, 2]
def bind(cls):
reg['hdlgen/map'] = {}
reg['hdlgen/hdlmods'] = {}
reg['hdlgen/disambig'] = {}
register_custom_log('svgen', logging.WARNING)
reg.confdef('svgen/include', getter=svgen_include_get)
reg.confdef('vhdgen/include', [])
reg['vgen/map'] = {}
register_custom_log('vgen', logging.WARNING)
reg.confdef('vgen/include', getter=vgen_include_get)
def bind(cls):
global gear_reg, sim_reg
gear_reg = {}
sim_reg = {}
reg['sim/config'] = {}
reg['sim/flow'] = []
reg['sim/tasks'] = {}
reg['sim/simulator'] = None
reg['sim/dryrun'] = False
reg.confdef('sim/rand_seed', None)
reg.confdef('sim/clk_freq', 1000)
reg.confdef('results-dir', default=tempfile.mkdtemp())
reg.confdef('sim/extens', default=[])
reg['gear/params/meta/sim_setup'] = None
register_custom_log('sim', cls=SimLog)
# temporary hack for pytest logger reset issue
reg['logger/sim/error'] = 'exception'
reg['logger/sim/print_traceback'] = False
def bind(cls):
reg.confdef('sim/svsock/backend', default={})
reg.confdef('sim/svsock/run', default=True)
reg['sim/svsock/intfs'] = []
reg['sim/svsock/server'] = None
def bind(cls):
reg.confdef('sim/aux_clock', default=[])
def bind(cls):
reg.confdef('debug/webviewer', setter=websim_activate, default=False)
def bind(cls):
reg.confdef('wavejson/trace_fn', 'pygears.json')