def construct(s, num_cores=1):
super().construct(num_cores)
# The translated Verilog must be xRTL.v instead of xPRTL.v
s.config_verilog_translate = TranslationConfigs(
translate=False,
explicit_module_name=f'proc_ProcRTL_{num_cores}core',
)
def construct(s, DataType):
# Port-based interface
s.in0 = InPort(DataType)
s.in1 = InPort(DataType)
s.out_min = OutPort(DataType)
s.out_max = OutPort(DataType)
# Configurations
s.config_placeholder = VerilogPlaceholderConfigs(
# Path to the Verilog source file
src_file=os.path.dirname(__file__) + '/MinMaxUnit.v',
# Name of the Verilog top level module
top_module='tut4_verilog_sort_MinMaxUnit',
# MinMaxUnit does not have clk and reset pins
has_clk=False,
has_reset=False,
# Verilog Parameters
params={'p_nbits': DataType.nbits},
)
s.config_verilog_translate = TranslationConfigs(
translate=False,
explicit_module_name='MinMaxUnit',
)
def construct( s ):
# clock (in PyMTL simulation it uses implict .clk port when
# translated to Verilog, actual clock ports should be CE1
s.CE1 = InPort () # clk
s.WEB1 = InPort () # bar( write en )
s.OEB1 = InPort () # bar( out en )
s.CSB1 = InPort () # bar( whole SRAM en )
s.A1 = InPort ( Bits8 ) # address
s.I1 = InPort ( Bits32 ) # write data
s.O1 = OutPort( Bits32 ) # read data
# instantiate a generic sram inside
s.sram_generic = SramGenericPRTL( 32, 256 )(
CE1 = s.CE1,
WEB1 = s.WEB1,
OEB1 = s.OEB1,
CSB1 = s.CSB1,
A1 = s.A1,
I1 = s.I1,
O1 = s.O1
)
s.config_verilog_translate = TranslationConfigs(
translate = False,
no_synthesis = True,
)
def construct(s,image_column,image_row, window_size,window_size_ext):
super().construct(image_column,image_row, window_size,window_size_ext)
# The translated Verilog must be xRTL.v instead of xPRTL.v
s.config_verilog_translate = TranslationConfigs(
translate=False,
explicit_module_name = f'Optical_flowRTL',
)
def construct(s):
# Interface
s.minion = MinionIfcRTL(GcdUnitMsgs.req, GcdUnitMsgs.resp)
# Configurations
s.config_placeholder = VerilogPlaceholderConfigs(
# Path to the Verilog source file
src_file=os.path.dirname(__file__) + '/GcdUnitRTL.v',
# Name of the Verilog top level module
top_module='tut4_verilog_gcd_GcdUnitRTL',
# Port name map
port_map={
'minion.req.en': 'req_en',
'minion.req.rdy': 'req_rdy',
'minion.req.msg': 'req_msg',
'minion.resp.en': 'resp_en',
'minion.resp.rdy': 'resp_rdy',
'minion.resp.msg': 'resp_msg',
},
)
s.config_verilog_import = VerilatorImportConfigs(
# Enable native Verilog line trace through Verilator
vl_line_trace=True, )
s.config_verilog_translate = TranslationConfigs(
translate=False,
explicit_module_name='GcdUnitRTL',
)
def construct(s, nstages=2):
super().construct(nstages)
# The translated Verilog must be xRTL.v instead of xPRTL.v
s.config_verilog_translate = TranslationConfigs(
translate=False,
explicit_module_name=f'lab1_imul_IntMulNstageRTL_{nstages}stages',
)
def construct(s):
super().construct()
# The translated Verilog must be xRTL.v instead of xPRTL.v
s.config_verilog_translate = TranslationConfigs(
translate=False,
explicit_module_name='SramMinionRTL',
)
def construct(s):
super().construct()
# The translated Verilog must be xRTL.v instead of xPRTL.v
s.config_verilog_translate = TranslationConfigs(
translate=False,
explicit_module_name=f'lab2_xcel_SortXcelRTL',
)
def construct(s):
super().construct()
# The translated Verilog must be xRTL.v instead of xPRTL.v
s.config_verilog_translate = TranslationConfigs(
translate=False,
explicit_module_name='lab1_imul_IntMulNstageStepRTL',
)
def construct(s, data_nbits=32, num_entries=256):
super().construct(data_nbits, num_entries)
# The translated Verilog must be xRTL.v instead of xPRTL.v
s.config_verilog_translate = TranslationConfigs(
translate=False,
explicit_module_name=
f'sram_SramRTL_{data_nbits}b_{num_entries}words',
)
def construct(s, num_banks=0):
super().construct(num_banks)
# The translated Verilog must be xRTL.v instead of xPRTL.v
s.config_verilog_translate = TranslationConfigs(
translate=False,
explicit_module_name=f'cache_BlockingCacheRTL_{num_banks}bank',
)
def traverse(m):
nonlocal tr_cfgs
if not hasattr( m, 'config_yosys_translate' ) or \
isinstance( m.config_yosys_translate, bool ):
tr_cfgs[m] = TranslationConfigs()
else:
tr_cfgs[m] = m.config_yosys_translate
for _m in m.get_child_components():
traverse(_m)
def construct( s, nports, nbits ):
s.in_ = InPort( mk_bits(nbits * nports) )
s.out = OutPort( mk_bits(nbits * nports) )
s.out //= s.in_
s.config_verilog_translate = TranslationConfigs(
# You can leave this option unset if your rtl_language is Verilog
translate = False,
# Use the xRTL module name instead of xPRTL
explicit_module_name = 'PassThroughV2RTL',
)
def construct(s, nports, nbits):
s.in_ = [InPort(mk_bits(nbits)) for _ in range(nports)]
s.out = [OutPort(mk_bits(nbits)) for _ in range(nports)]
for i in range(nports):
s.out[i] //= s.in_[i]
s.config_verilog_translate = TranslationConfigs(
# You can leave this option unset if your rtl_language is Verilog
translate=False,
# Use the xRTL module name instead of xPRTL
explicit_module_name='PassThroughV1RTL',
)
def construct(s):
s.in_ = InPort(Bits32)
s.out = OutPort(Bits32)
s.config_placeholder = VerilogPlaceholderConfigs(
src_file=dirname(__file__) + '/VReg.v',
port_map={
"clk": "clk",
"reset": "reset",
"in_": "d",
"out": "q",
})
s.config_verilog_translate = TranslationConfigs(
explicit_module_name='VReg_imported', )
s.verilog_translate_import = True
def construct(s, nbits=8):
DataType = mk_bits(nbits)
#---------------------------------------------------------------------
# Interface
#---------------------------------------------------------------------
s.in_val = InPort()
s.in_ = [InPort(DataType) for _ in range(4)]
s.out_val = OutPort()
s.out = [OutPort(DataType) for _ in range(4)]
#---------------------------------------------------------------------
# Configurations
#---------------------------------------------------------------------
s.config_placeholder = VerilogPlaceholderConfigs(
# Path to the Verilog source file
src_file=os.path.dirname(__file__) + '/SortUnitStructRTL.v',
# Name of the Verilog top level module
top_module='tut4_verilog_sort_SortUnitStructRTL',
# Parameters of the Verilog module
params={'p_nbits': nbits},
# Port name map
port_map={
'in_val': 'in_val',
'in_[0]': 'in0',
'in_[1]': 'in1',
'in_[2]': 'in2',
'in_[3]': 'in3',
'out_val': 'out_val',
'out[0]': 'out0',
'out[1]': 'out1',
'out[2]': 'out2',
'out[3]': 'out3',
},
)
s.config_verilog_import = VerilatorImportConfigs(
# Enable native Verilog line trace through Verilator
vl_line_trace=False, )
s.config_verilog_translate = TranslationConfigs(
translate=False,
explicit_module_name=f'SortUnitStructRTL_{nbits}bit',
)
def construct(s):
s.imm_type = InPort(Bits3)
s.inst = InPort(Bits32)
s.imm = OutPort(Bits32)
# Verilog module setup
s.config_placeholder = VerilogPlaceholderConfigs(
src_file=path.dirname(__file__) + '/ProcDpathComponentsVRTL.v',
top_module='proc_ImmGenVRTL',
has_clk=False,
has_reset=False,
)
s.config_verilog_translate = TranslationConfigs(
translate=False,
explicit_module_name='proc_ImmGenRTL',
)
def construct(s, side):
# Interface
s.en = InPort(Bits1)
s.current_frame = [
InPort(mk_bits(32)) for _ in range((side + 2) * (side + 2))
]
s.next_frame = [
InPort(mk_bits(32)) for _ in range((side + 2) * (side + 2))
]
s.Ix = [OutPort(mk_bits(32)) for _ in range(side * side)]
s.Iy = [OutPort(mk_bits(32)) for _ in range(side * side)]
s.It = [OutPort(mk_bits(32)) for _ in range(side * side)]
s.valid = OutPort(Bits1)
#s.in_ = InPort (Bits8)
#s.out = OutPort (Bits4)
# Configurations
from os import path
s.config_placeholder = VerilogPlaceholderConfigs(
# Path to the Verilog source file
src_file=path.dirname(__file__) + '/GradientVRTL.v',
#src_file = path.dirname(__file__) + '/IntMulVarLatCalcShamtVRTL.v',
# Name of the Verilog top level module
top_module='GradientVRTL',
#top_module = 'lab1_imul_IntMulVarLatCalcShamtVRTL',
# Step unit does not have clk and reset pins
params={
'side': side,
},
has_clk=False,
has_reset=False,
)
#edit here
s.config_verilog_translate = TranslationConfigs(
# You can leave this option unset if your rtl_language is Verilog
translate=False,
# Use the xRTL module name instead of xVRTL
explicit_module_name=f'Gradient',
)
def construct(s):
# Interface
s.req_go = InPort(mk_bits(1))
s.in_x = [InPort(mk_bits(32)) for _ in range(9)]
s.in_y = [InPort(mk_bits(32)) for _ in range(9)]
s.in_t = [InPort(mk_bits(32)) for _ in range(9)]
s.vx = OutPort(mk_bits(32))
s.vy = OutPort(mk_bits(32))
s.de = OutPort(mk_bits(32))
s.result_ok = OutPort(mk_bits(32))
#s.req_msg_a=InPort(Bits32)
#s.req_msg_b=InPort(Bits1)
#s.presum =InPort(Bits32)
#s.resp_msg =OutPort(Bits32)
#s.a_shift =OutPort(Bits32)
#s.in_ = InPort (Bits8)
#s.out = OutPort (Bits4)
# Configurations
from os import path
s.config_placeholder = VerilogPlaceholderConfigs(
# Path to the Verilog source file
src_file=path.dirname(__file__) + '/matrix_operaVRTL.v',
#src_file = path.dirname(__file__) + '/IntMulVarLatCalcShamtVRTL.v',
# Name of the Verilog top level module
top_module='matrix_operaVRTL',
#top_module = 'lab1_imul_IntMulVarLatCalcShamtVRTL',
# Step unit does not have clk and reset pins
params={},
has_clk=True,
has_reset=True,
)
#edit here
s.config_verilog_translate = TranslationConfigs(
# You can leave this option unset if your rtl_language is Verilog
translate=False,
# Use the xRTL module name instead of xVRTL
explicit_module_name=f'matrix_opera',
)
def construct(s):
s.in0 = InPort(Bits32)
s.in1 = InPort(Bits32)
s.fn = InPort(Bits4)
s.out = OutPort(Bits32)
s.ops_eq = OutPort()
s.ops_lt = OutPort()
s.ops_ltu = OutPort()
# Verilog module setup
s.config_placeholder = VerilogPlaceholderConfigs(
src_file=path.dirname(__file__) + '/ProcDpathComponentsVRTL.v',
top_module='proc_AluVRTL',
has_clk=False,
has_reset=False,
)
s.config_verilog_translate = TranslationConfigs(
translate=False,
explicit_module_name='proc_AluRTL',
)
def construct( s ):
s.a = InPort(Bits32)
s.b = InPort(Bits4)
s.result = OutPort(Bits32)
# Instantiate steps
s.steps = [ IntMulNstageStepRTL() for _ in range(4) ]
# Structural composition for first step
s.steps[0].in_b //= lambda: zext(s.b, 32)
s.steps[0].in_en //= 1
s.steps[0].in_a //= s.a
s.steps[0].in_result //= 0
# Structural composition for intermediate steps
for i in range(3):
s.steps[i+1].in_en //= s.steps[i].out_en
s.steps[i+1].in_a //= s.steps[i].out_a
s.steps[i+1].in_b //= s.steps[i].out_b
s.steps[i+1].in_result //= s.steps[i].out_result
# Structural composition for last step
s.steps[3].out_result //= s.result
# Configuration setting
for i in range(4):
s.steps[i].config_verilog_translate = TranslationConfigs(
translate = False,
explicit_module_name = f'IntMulNstageStepRTL__steps_{i}',
)
def construct(s, nports, nbits):
s.in_ = InPort(mk_bits(nbits * nports))
s.out = OutPort(mk_bits(nbits * nports))
from os import path
s.config_placeholder = VerilogPlaceholderConfigs(
src_file=path.dirname(__file__) + '/PassThroughV2VRTL.v',
# If the top module name is the same as the component class
# name it is safe to not set it.
# top_module = 'PassThroughV2VRTL',
params={
'num_ports': nports,
'bitwidth': nbits,
},
# The Verilog module does not have clk and reset
has_clk=False,
has_reset=False,
)
s.config_verilog_translate = TranslationConfigs(
# You can leave this option unset if your rtl_language is Verilog
translate=False,
# Use the xRTL module name instead of xVRTL
explicit_module_name='PassThroughV2RTL',
)
