def check_valid(s, m, cfg, irepr):
pmap, src, flist, include = \
cfg.port_map, cfg.src_file, cfg.v_flist, cfg.v_include
# Check params
for param_name, value in cfg.params.items():
if not isinstance(value, int):
raise InvalidPassOptionValue(
"params", cfg.params, cfg.Pass.__name__,
f"non-integer parameter {param_name} is not supported yet!"
)
# Check port map
# TODO: this should be based on RTLIR
for port in pmap.keys():
if port.get_host_component() is not m:
raise InvalidPassOptionValue(
"port_map", pmap, cfg.Pass.__name__,
f"Port {port} does not exist in component {irepr.get_name()}!"
)
# Check src_file
if cfg.src_file and not os.path.isfile(expand(cfg.src_file)):
raise InvalidPassOptionValue("src_file", cfg.src_file,
cfg.Pass.__name__,
'src_file should be a file path!')
if cfg.v_flist:
raise InvalidPassOptionValue(
"v_flist", cfg.v_flist, cfg.Pass.__name__,
'Placeholders backed by Verilog flist are not supported yet!')
# Check v_flist
if cfg.v_flist and not os.path.isfile(expand(cfg.v_flist)):
raise InvalidPassOptionValue("v_flist", cfg.v_flist,
cfg.Pass.__name__,
'v_flist should be a file path!')
# Check v_include
if cfg.v_include:
for include in cfg.v_include:
if not os.path.isdir(expand(include)):
raise InvalidPassOptionValue(
"v_include", cfg.v_include, cfg.Pass.__name__,
'v_include should be an array of dir paths!')
# Check if the top module name appears in the file
if cfg.src_file:
found = False
with open(cfg.src_file) as src_file:
for line in src_file.readlines():
if cfg.top_module in line:
found = True
break
if not found:
raise InvalidPassOptionValue(
"top_module", cfg.top_module, cfg.Pass.__name__,
f'cannot find top module {cfg.top_module} in source file {cfg.src_file}.\n'
f'Please make sure you have specified the correct top module name through '
f'the VerilogPlaceholderPass.top_module pass data name!')
def _import_sources(s, cfg, source_list):
# Import Verilog source from all Verilog files source_list. This includes
# any source files specified by `include within those files.
code = ""
if not source_list:
return
# We will use the first verilog file to find the root of PyMTL project
first_verilog_file = source_list[0]
# All verilog includes are relative to the root of the PyMTL project.
# We identify the root of the PyMTL project by looking for the special
# pymtl.ini file.
_path = os.path.dirname(first_verilog_file)
special_file_found = False
include_path = os.path.dirname(os.path.abspath(first_verilog_file))
while include_path != "/":
if os.path.exists(include_path + os.path.sep + "pymtl.ini"):
special_file_found = True
sys.path.insert(0, include_path)
break
include_path = os.path.dirname(include_path)
# Append the user-defined include path to include_path
# NOTE: the current pickler only supports one include path. If v_include
# config is present, use it instead.
if cfg.v_include:
if len(cfg.v_include) != 1:
raise InvalidPassOptionValue(
"v_include", cfg.v_include, cfg.Pass.__name__,
'the current pickler only supports one user-defined v_include path...'
)
include_path = cfg.v_include[0]
# If we could not find the special .pymtl-python-path file, then assume
# the include directory is the same as the directory that contains the
# first verilog file.
if not special_file_found and not cfg.v_include:
include_path = os.path.dirname(os.path.abspath(first_verilog_file))
# Regex to extract verilog filenames from `include statements
s._include_re = re.compile(r'"(?P<filename>[\w/\.-]*)"')
# Iterate through all source files and add any `include files to the
# list of source files to import.
for source in source_list:
code += s._output_verilog_file(include_path, source)
return code
def get_vl_xinit_value( s ):
if s.vl_xinit == 'zeros':
return 0
elif s.vl_xinit == 'ones':
return 1
elif ( s.vl_xinit == 'rand' ) or isinstance( s.vl_xinit, int ):
return 2
else:
raise InvalidPassOptionValue("vl_xinit should be an int or one of 'zeros', 'ones', or 'rand'!")
def check_p_map(s, rtype):
"""Check if each port name of `rtype` is in port map."""
pm = s.get_option("port_map")
all_ports = rtype.get_ports_packed()
assert all(isinstance(p, rt.Port) and \
isinstance(p.get_dtype(), rdt.Vector) for n, p in all_ports), \
f"Port map option currently requires all ports of {rtype.get_name()}"\
f" to be a single vector port."
for name, port in all_ports:
if name not in pm:
raise InvalidPassOptionValue(
"port_map", pm, s.PassName,
f"Port {name} of {rtype.get_name()} should be mapped to a new name!"
)
if len(all_ports) != len(pm):
raise InvalidPassOptionValue(
"port_map", pm, s.PassName,
f"All ports of {rtype.get_name()} should be mapped to a new name!"
)
def check_valid(s, m, cfg, irepr):
pmap, src, flist, include = \
cfg.port_map, cfg.src_file, cfg.v_flist, cfg.v_include
# Check params
for param_name, value in cfg.params.items():
if not isinstance(value, int):
raise InvalidPassOptionValue(
"params", cfg.params, cfg.PassName,
f"non-integer parameter {param_name} is not supported yet!"
)
# Check port map
# TODO: this should be based on RTLIR
# unmapped_unpacked_ports = gen_unpacked_ports( irepr )
# unmapped_port_names = list(map(lambda x: x[0], list(unmapped_unpacked_ports)))
# for name in pmap.keys():
# if name not in unmapped_port_names:
# raise InvalidPassOptionValue("port_map", pmap, cfg.PassName,
# f"Port {name} does not exist in component {irepr.get_name()}!")
for name in pmap.keys():
try:
eval(f'm.{name}')
except:
raise InvalidPassOptionValue(
"port_map", pmap, cfg.PassName,
f"Port {name} does not exist in component {irepr.get_name()}!"
)
# Check src_file
if cfg.src_file and not os.path.isfile(expand(cfg.src_file)):
raise InvalidPassOptionValue("src_file", cfg.src_file,
cfg.PassName,
'src_file should be a file path!')
if cfg.v_flist:
raise InvalidPassOptionValue(
"v_flist", cfg.v_flist, cfg.PassName,
'Placeholders backed by Verilog flist are not supported yet!')
# Check v_flist
if cfg.v_flist and not os.path.isfile(expand(cfg.v_flist)):
raise InvalidPassOptionValue("v_flist", cfg.v_flist, cfg.PassName,
'v_flist should be a file path!')
# Check v_include
if cfg.v_include:
for include in cfg.v_include:
if not os.path.isdir(expand(include)):
raise InvalidPassOptionValue(
"v_include", cfg.v_include, cfg.PassName,
'v_include should be an array of dir paths!')