def run_sim(s, th, gen_test, max_cycles=10000):
th.elaborate()
# Assemble the program
mem_image = assemble(gen_test())
# Load the program into memory
th.load(mem_image)
# Translate the processor and import it back in
from pymtl3.passes.yosys import TranslationImportPass
th.proc.yosys_translate_import = True
th = TranslationImportPass()(th)
# Create a simulator and run simulation
th.apply(SimulationPass)
th.sim_reset()
print()
ncycles = 0
while not th.done() and ncycles < max_cycles:
th.tick()
print("{:3}: {}".format(ncycles, th.line_trace()))
ncycles += 1
# Force a test failure if we timed out
assert ncycles < max_cycles
def local_do_test( _m ):
try:
_m.elaborate()
_m.yosys_translate_import = True
m = TranslationImportPass()( _m )
sim = TestVectorSimulator( m, _m._test_vectors, _m._tv_in, _m._tv_out )
sim.run_test()
finally:
try:
m.finalize()
except UnboundLocalError:
# This test fails due to translation errors
pass
def local_do_test(_m):
try:
_m.elaborate()
# Mark component `_m` as to be translated and imported
_m.yosys_translate_import = True
m = TranslationImportPass()(_m)
sim = TestVectorSimulator(m, _m._test_vectors, _m._tv_in, _m._tv_out)
sim.run_test()
finally:
try:
# Explicitly finalize imported component to avoid shared lib name aliasing
m.finalize()
except UnboundLocalError:
# This test fails due to translation errors
pass
def checksum_vrtl( words ):
# Convert input words into bits
bits_in = words_to_b128( words )
# Instantiate and elaborate the checksum unit
dut = ChecksumRTL()
dut.elaborate()
# Translate the checksum unit and import it back in using the yosys
# backend
dut.yosys_translate_import = True
dut = TranslationImportPass()( dut )
# Create a simulator
dut.elaborate()
dut.apply( SimulationPass )
dut.sim_reset()
# Wait until the checksum unit is ready to receive input
dut.send.rdy = b1(1)
while not dut.recv.rdy:
dut.tick()
# Feed in the input
dut.recv.en = b1(1)
dut.recv.msg = bits_in
dut.tick()
# Wait until the checksum unit is about to send the message
while not dut.send.en:
dut.tick()
# Return the result
return dut.send.msg
def test_rtl():
dut = GCDUnitRTL(b8)
dut.elaborate()
dut.yosis_translate_import = True
dut = TranslationImportPass()(dut)
# Create a simulator
dut.dump_vcd = True
dut.vcd_file_name = "gcd"
dut.elaborate()
dut.apply(SimulationPass)
dut.sim_reset()
randA = random.randint(0, 255)
dut.in_a = b8(randA)
print(randA)
randB = random.randint(0, 255)
dut.in_b = b8(randB)
print(randB)
dut.reset = b1(1)
dut.tick()
dut.reset = b1(0)
dut.tick()
assert dut.out == gcd(randA, randB)
def checksum_xcel_vrtl(words):
assert len(words) == 8
# Create a simulator using RTL accelerator
dut = ChecksumXcelRTL()
dut.elaborate()
# Translate the checksum unit and import it back in using the yosys
# backend
dut.yosys_translate_import = True
dut = TranslationImportPass()(dut)
# Create a simulator
dut.elaborate()
dut.apply(SimulationPass)
dut.sim_reset()
reqs, _ = mk_xcel_transaction(words)
for req in reqs:
# Wait until xcel is ready to accept a request
dut.xcel.resp.rdy = b1(1)
while not dut.xcel.req.rdy:
dut.xcel.req.en = b1(0)
dut.tick()
# Send a request
dut.xcel.req.en = b1(1)
dut.xcel.req.msg = req
dut.tick()
# Wait for response
while not dut.xcel.resp.en:
dut.xcel.req.en = b1(0)
dut.tick()
# Get the response message
resp_data = dut.xcel.resp.msg.data
dut.tick()
return resp_data
def test_rtl():
dut = BresenhamUnitRTL(b6)
dut.elaborate()
dut.yosis_translate_import = True
dut = TranslationImportPass()(dut)
# Create a simulator
dut.dump_vcd = True
dut.vcd_file_name = "Bresenham"
dut.elaborate()
dut.apply(SimulationPass)
dut.sim_reset()
for i in range(1, 100):
randA = random.randint(1, 32)
randB = random.randint(1, 32)
randC = random.randint(1, 32)
randD = random.randint(1, 32)
dut.x0 = b6(randA)
dut.y0 = b6(randB)
dut.x1 = b6(randC)
dut.y1 = b6(randD)
print('x0:', randA, 'y0:', randB, 'x1:', randC, 'y1:', randD)
dut.tick()
dut.trigger = b1(1)
dut.tick()
dut.trigger_i = b1(0)
while dut.valid == b1(0):
dut.tick()
print('output_x: ', "%d" % (dut.output_x))
print('output_y: ', "%d" % (dut.output_y))
print('')
result = line2(randA, randB, randC, randD)
assert dut.output_x == result[0]
assert dut.output_y == result[1]
def test_rtl():
dut = PrngUnit(b32)
dut.elaborate()
dut.yosis_translate_import = True
dut = TranslationImportPass()(dut)
# Create a simulator
dut.dump_vcd = True
dut.vcd_file_name = "PRNG"
dut.elaborate()
dut.apply(SimulationPass)
dut.sim_reset()
randA = random.randint(0, 4294967295)
# dut.input = b32(3904692793)
dut.input = b32(randA)
print('RTL input :', "%d" % (dut.input))
for i in range(1, 10):
dut.tick()
dut.input = dut.output
print('RTL output', i, ':', "%d" % (dut.input))
assert dut.output == prng(
prng(prng(prng(prng(prng(prng(prng(prng(randA)))))))))
def test_rtl():
dut = FibonacciUnit(b16)
dut.elaborate()
dut.yosis_translate_import = True
dut = TranslationImportPass()(dut)
# Create a simulator
dut.dump_vcd = True
dut.vcd_file_name = "fibonacci"
dut.elaborate()
dut.apply(SimulationPass)
dut.sim_reset()
randA = random.randint(0, 15)
dut.input = b8(randA)
print(randA)
dut.trigger = b1(1)
dut.tick()
dut.trigger = b1(0)
dut.tick()
print(dut.output)
assert dut.output == fib(randA)
def run_sim(s, th, max_cycles=1000):
# Translate the DUT and import it back in using the yosys backend.
th.elaborate()
th.dut.yosys_translate_import = True
th = TranslationImportPass()(th)
# Create a simulator
th.apply(SimulationPass)
ncycles = 0
th.sim_reset()
print("")
# Tick the simulator
print("{:3}: {}".format(ncycles, th.line_trace()))
while not th.done() and ncycles < max_cycles:
th.tick()
ncycles += 1
print("{:3}: {}".format(ncycles, th.line_trace()))
# Check timeout
assert ncycles < max_cycles
def run_sim( s, th, max_cycles=1000 ):
# Check command line arguments for vcd dumping
if s.vcd_file_name:
th.dump_vcd = True
th.vcd_file_name = "translated."+s.vcd_file_name
# Translate the DUT and import it back in using the yosys backend.
th.elaborate()
th.dut.yosys_translate_import = True
# ''' TUTORIAL TASK ''''''''''''''''''''''''''''''''''''''''''''''''''
# Apply the translation-import and simulation passes
# ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''\/
th = TranslationImportPass()( th )
th.apply( SimulationPass )
# ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''/\
ncycles = 0
th.sim_reset()
print( "" )
# Tick the simulator
print("{:3}: {}".format( ncycles, th.line_trace() ))
while not th.done() and ncycles < max_cycles:
th.tick()
ncycles += 1
print("{:3}: {}".format( ncycles, th.line_trace() ))
# Check timeout
assert ncycles < max_cycles
def run_sim(_th):
try:
_th.elaborate()
_th.q.yosys_translate_import = True
th = TranslationImportPass()(_th)
th.apply(DynamicSim)
print()
cycle = 0
while not th.done() and cycle < 1000:
th.tick()
print(th.line_trace())
cycle += 1
assert cycle < 1000
th.tick()
th.tick()
th.tick()
finally:
try:
th.q.finalize()
except UnboundLocalError:
# This test fails due to translation errors
pass