def construct( s, proc_cls, xcel_cls=NullXcelRTL, dump_vcd=False,
src_delay=0, sink_delay=0,
mem_stall_prob=0, mem_latency=1 ):
s.commit_inst = OutPort( Bits1 )
req, resp = mk_mem_msg( 8, 32, 32 )
s.src = TestSrcCL ( Bits32, [], src_delay, src_delay )
s.sink = TestSinkCL( Bits32, [], sink_delay, sink_delay )
s.proc = proc_cls()
s.xcel = xcel_cls()
s.mem = MemoryCL(2, latency = mem_latency)
connect_pairs(
s.proc.commit_inst, s.commit_inst,
# Processor <-> Proc/Mngr
s.src.send, s.proc.mngr2proc,
s.proc.proc2mngr, s.sink.recv,
# Processor <-> Memory
s.proc.imem, s.mem.ifc[0],
s.proc.dmem, s.mem.ifc[1],
)
connect( s.proc.xcel, s.xcel.xcel )
def construct(s, xcel):
s.tm = TestMasterCL(XcelMsgs.req, XcelMsgs.resp, XcelMasterIfcCL)
s.mem = MemoryCL(1)
s.xcel = xcel
s.tm.master //= s.xcel.xcel
s.mem.ifc[0] //= s.xcel.mem
def construct( s, dut, check_test ):
# Instantiate models
s.src = TestSrcCL( CacheReqType )
s.cache = dut
s.mem = MemoryCL( 1, [ (MemReqType, MemRespType) ] )
s.sink = TestCacheSink( CacheRespType, check_test=check_test )
# Connect
s.src.send //= s.cache.cache.req
s.sink.recv //= s.cache.cache.resp
s.cache.mem //= s.mem.ifc[0]
def construct(s,
src_msgs,
sink_msgs,
stall_prob,
latency,
src_delay,
sink_delay,
CacheModel,
CacheReqType,
CacheRespType,
MemReqType,
MemRespType,
cacheSize=128,
associativity=1):
# Instantiate models
s.src = TestSrcRTL(CacheReqType, src_msgs, 0, src_delay)
s.proc_model = ProcModel(CacheReqType, CacheRespType)
s.cache = CacheModel(CacheReqType, CacheRespType, MemReqType,
MemRespType, cacheSize, associativity)
s.mem = MemoryCL(1, [(MemReqType, MemRespType)],
latency) # Use our own modified mem
s.cache2mem = RecvRTL2SendCL(MemReqType)
s.mem2cache = RecvCL2SendRTL(MemRespType)
s.sink = TestSinkRTL(CacheRespType, sink_msgs, 0, sink_delay)
# Set the test signals to better model the processor
# Connect the src and sink to model proc
s.src.send //= s.proc_model.proc.req
s.sink.recv //= s.proc_model.proc.resp
# Connect the proc model to the cache
s.proc_model.cache //= s.cache.mem_minion_ifc
# Connect the cache req and resp ports to test memory
connect(s.mem.ifc[0].resp, s.mem2cache.recv)
connect(s.cache.mem_master_ifc.resp, s.mem2cache.send)
connect(s.cache.mem_master_ifc.req, s.cache2mem.recv)
connect(s.mem.ifc[0].req, s.cache2mem.send)
def construct( s, proc_cls, xcel_cls, dump_vcd,
src_delay, sink_delay,
mem_stall_prob, mem_latency ):
s.commit_inst = OutPort( Bits1 )
req, resp = mk_mem_msg( 8, 32, 32 )
s.src = TestSrcCL ( Bits32, [], src_delay, src_delay )
s.sink = TestSinkCL( Bits32, [], sink_delay, sink_delay )
s.dut = ProcXcel( proc_cls, xcel_cls )( commit_inst = s.commit_inst )
s.mem = MemoryCL(2, latency = mem_latency)
connect_pairs(
# Processor <-> Proc/Mngr
s.src.send, s.dut.mngr2proc,
s.dut.proc2mngr, s.sink.recv,
# Processor <-> Memory
s.proc.imem, s.mem.ifc[0],
s.proc.dmem, s.mem.ifc[1],
)
def construct(s, proc_cls):
s.commit_inst = OutPort()
s.src = TestSrcCL(Bits32, [])
s.sink = TestSinkCL(Bits32, [])
s.proc = proc_cls()
s.xcel = NullXcelRTL()
s.mem = MemoryCL(2)
s.proc.commit_inst //= s.commit_inst
# Processor <-> Proc/Mngr
s.src.send //= s.proc.mngr2proc
s.proc.proc2mngr //= s.sink.recv
# Processor <-> Memory
s.proc.imem //= s.mem.ifc[0]
s.proc.dmem //= s.mem.ifc[1]
s.proc.xcel //= s.xcel.xcel
# Starting F16 we turn core_id into input ports to
# enable module reusability. In the past it was passed as arguments.
s.proc.core_id //= 0
def __init__(s,
src_msgs,
sink_msgs,
stall_prob,
latency,
src_delay,
sink_delay,
CacheModel,
check_test,
dump_vcd,
test_verilog=False):
# Messge type
cache_msgs = MemMsg4B()
mem_msgs = CoherentMemMsg16B()
# Instantiate models
s.src = TestSrcCL(cache_msgs.req, src_msgs, src_delay)
s.cache = CacheModel(ncaches=1, cache_id=0)
s.mem = MemoryCL(mem_msgs, 1, stall_prob, latency)
s.sink = TestSinkCL(cache_msgs.resp, sink_msgs, sink_delay, check_test)
# Dump VCD
if dump_vcd:
s.cache.vcd_file = dump_vcd
# Verilog translation
if test_verilog:
s.cache = TranslationTool(s.cache, enable_blackbox=True)
# Proc -> Cache
s.cachereq = InValRdyIfc(MemReqMsg4B)
# Mem -> Cache
s.memresp = InValRdyIfc(CoherentMemRespMsg16B)
# Cache -> Proc
s.cacheresp = OutValRdyIfc(MemRespMsg4B)
# Cache -> Mem
s.memreq = OutValRdyIfc(CoherentMemReqMsg16B)
# Mem -> Cache (fwdreq)
s.fwdreq = InValRdyIfc(CoherentMemReqMsg16B)
# Cache -> Mem (fwdresp)
s.fwdresp = OutValRdyIfc(CoherentMemRespMsg16B)
# Connect
s.connect_pairs(
# cachereq
s.cache.cachereq_val,
s.cachereq.val,
s.cache.cachereq_rdy,
s.cachereq.rdy,
s.cache.cachereq_msg,
s.cachereq.msg,
# memresp
s.cache.memresp_val,
s.memresp.val,
s.cache.memresp_rdy,
s.memresp.rdy,
s.cache.memresp_msg,
s.memresp.msg,
# cacheresp
s.cache.cacheresp_val,
s.cacheresp.val,
s.cache.cacheresp_rdy,
s.cacheresp.rdy,
s.cache.cacheresp_msg,
s.cacheresp.msg,
# memreq
s.cache.memreq_val,
s.memreq.val,
s.cache.memreq_rdy,
s.memreq.rdy,
s.cache.memreq_msg,
s.memreq.msg,
# fwdreq
s.cache.fwdreq_val,
s.fwdreq.val,
s.cache.fwdreq_rdy,
s.fwdreq.rdy,
s.cache.fwdreq_msg,
s.fwdreq.msg,
# fwdresp
s.cache.fwdresp_val,
s.fwdresp.val,
s.cache.fwdresp_rdy,
s.fwdresp.rdy,
s.cache.fwdresp_msg,
s.fwdresp.msg,
)
s.connect(s.src.out, s.cachereq)
s.connect(s.sink.in_, s.cacheresp)
s.connect(s.memreq, s.mem.reqs[0])
s.connect(s.memresp, s.mem.resps[0])