def _printexpr_operator(node, ctx):
thint = get("thint", ctx)
arity = len(node.operands)
if arity == 1:
r1 = _printexpr(node.operands[0],
merge(ctx, dict(lhs=False,
thint=_THint.logic,
lhint=None)))
if node.op == "-":
expr = "(-{})".format(_signed(r1))
if thint == _THint.un_signed:
return expr
elif thint == _THint.integer:
return _to_integer(expr)
elif thint == _THint.logic:
return _std_logic_vector(expr)
else:
return expr
else:
expr = "{} {}".format(_get_op(node), r1)
if thint == _THint.un_signed:
return _unsigned(expr)
elif thint == _THint.integer:
return _fn_call("to_integer", _unsigned(expr))
elif thint == _THint.boolean:
return _fn_call("\\??\\", expr)
else:
return "({})".format(expr)
elif arity == 2:
if _is_bitwise_op(node):
r1, r2 = pipe(
[node, ctx],
juxt([
comp(attrgetter("operands"), first),
comp(repeat, flip(merge, dict(lhs=False,
thint=_THint.logic,
lhint=None)), second),
]), R.apply(zip), map(R.apply(_printexpr)))
expr = pipe([r1, _get_op(node), r2], " ".join)
if thint == _THint.un_signed:
return _unsigned(expr)
elif thint == _THint.integer:
return _fn_call("to_integer", expr)
else:
return expr
elif _is_comp_op(node):
if pipe(node.operands, R.all_satisfy(comp(R.equals(1), len))):
r1, r2 = pipe(
[node, ctx],
juxt([
comp(attrgetter("operands"), first),
comp(repeat, flip(merge, dict(lhs=False,
thint=_THint.logic,
lhint=None)), second),
]), R.apply(zip), R.map(R.apply(_printexpr)))
else:
r1, r2 = pipe(
[node, ctx],
juxt([
comp(attrgetter("operands"), first),
comp(repeat, second)]), R.apply(zip),
map(juxt([
first,
comp(
R.apply(merge),
juxt([
second,
R.always(dict(lhs=False, lhint=None)),
R.if_else(
comp(R.isinstance(Constant), first),
R.always(dict(thint=_THint.integer)),
R.always(dict(thint=_THint.un_signed)))
]))])),
map(R.apply(_printexpr)))
if thint == _THint.logic:
return _fn_call(pipe(node, _get_op, "\\?{}\\".format), r1, r2)
else:
return pipe([r1, _get_op(node), r2], " ".join)
elif _is_shift_op(node):
r1, r2 = pipe(
[node, ctx],
juxt([
comp(attrgetter("operands"), first),
comp(repeat, second)]), R.apply(zip),
map(juxt([
first,
comp(
R.apply(merge),
juxt([
second,
R.always(dict(lhs=False, lhint=None)),
R.if_else(
comp(R.isinstance(Constant), first),
R.always(dict(thint=_THint.integer)),
R.always(dict(thint=_THint.un_signed)))
]))])),
map(R.apply(_printexpr)))
expr = _fn_call(_shift_op[node.op], r1, r2)
if thint == _THint.integer:
return _fn_call("to_integer", expr)
elif thint == _THint.logic:
return _std_logic_vector(expr)
else:
return expr
elif _is_arith_op(node):
r1, r2 = pipe(
node.operands,
map(lambda x:
_printexpr(x,
merge(ctx,
dict(lhs=False,
thint=_THint.integer
if R.isinstance(Constant, x)
else _THint.un_signed,
lhint=None)))))
expr = pipe([r1, _arith_op_map[node.op], r2], " ".join)
if thint == _THint.integer:
return _fn_call("to_integer", expr)
elif thint == _THint.logic:
return _std_logic_vector(expr)
else:
return expr
raise TypeError("unkown operator: {}, arity: {}".format(node, arity))
def __str__(self):
result = type(self).__name__ + '(' + self.value.__str__() + ')'
return result
def __repr__(self):
self.inc_level()
#result = "{}{}(\n{}\n{})\n".format(Base.level*'\t',type(self).__name__,type(self.value),Base.level*'\t')
result = type(self).__name__ + self.value.__repr__()
result = type(self).__name__ + '(' + self.value.__repr__() + ')'
self.dec_level()
#result = type(self).__name__ + '(\n' + self.value.__repr__() + '\n)'
return result
maybe_none = r.if_else(r.equals(None), r.always(md.Nothing), md.Just)
maybe_empty = r.if_else(lambda x: len(x) == 0, r.always(md.Nothing), md.Just)
@r.curry
def applymap(fn, x):
return x.applymap(fn)
@r.curry
def apply(fn, x):
return x.apply(fn)
def dropna(x):
return x.dropna
"generate", "generic", "group", "guarded", "if", "impure", "in", "inertial",
"inout", "is", "label", "library", "linkage", "literal", "loop", "map",
"mod", "nand", "new", "next", "nor", "not", "null", "of", "on", "open",
"or", "others", "out", "package", "parameter", "port", "postponed",
"procedure", "process", "property", "protected", "pure", "range", "record",
"register", "reject", "release", "rem", "report", "restruct",
"restrict_guarantee", "return", "rol", "ror", "select", "sequence",
"severity", "shared", "signal", "sla", "sll", "sra", "srl", "strong",
"subtype", "then", "to", "transport", "type", "unaffected", "units",
"until", "use", "variable", "vmode", "vprop", "vunit", "wait", "when",
"while", "whith", "xnor", "xor"}
_get_sigtype = R.if_else(
comp(R.equals(1), len),
R.always("std_ulogic"),
comp("std_logic_vector({} downto 0)".format, R.dec, len))
_sort_by_hash = partial(sorted, key=hash)
_sigs = comp(
R.apply(or_),
juxt([
list_signals,
partial(list_special_ios, ins=True, outs=True, inouts=True)]))
_inouts = partial(list_special_ios, ins=False, outs=False, inouts=True)
_targets = comp(
R.apply(or_),
juxt([
import toolz.curried as toolz
import pyramda as R
get_sigtype = R.if_else(
toolz.comp(R.equals(1), len), R.always("std_ulogic"),
toolz.comp("std_logic_vector({} downto 0)".format, R.dec, len))
flip(get)(dict([
(DIR_M_TO_S, "o_" if ps_m else "i_"),
(DIR_S_TO_M, "i_" if ps_m else "o_"),
(DIR_NONE, "io_")
])), get(-1))),
comp(operator.methodcaller("upper"), sig_name, first),
])), first
])), dict)
fix_arsize = comp(
R.apply(update_in),
juxt([
identity,
comp(list, filter(flip(str.endswith, "ARSIZE"))),
R.always(get(slice(-1))),
]))
fix_awsize = comp(
R.apply(update_in),
juxt([
identity,
comp(list, filter(flip(str.endswith, "AWSIZE"))),
R.always(get(slice(-1))),
]))
def connect_s_axi(interface):
return thread_first(interface, (connect_interface, False), fix_arsize,
fix_awsize)
def _printexpr_operator(node, ctx):
thint = get("thint", ctx)
arity = len(node.operands)
if arity == 1:
r1 = _printexpr(
node.operands[0],
merge(ctx, dict(lhs=False, thint=_THint.logic, lhint=None)))
if node.op == "-":
expr = "(-{})".format(_signed(r1))
if thint == _THint.un_signed:
return expr
elif thint == _THint.integer:
return _to_integer(expr)
elif thint == _THint.logic:
return _std_logic_vector(expr)
else:
return expr
else:
expr = "{} {}".format(_get_op(node), r1)
if thint == _THint.un_signed:
return _unsigned(expr)
elif thint == _THint.integer:
return _fn_call("to_integer", _unsigned(expr))
elif thint == _THint.boolean:
return _fn_call("\\??\\", expr)
else:
return "({})".format(expr)
elif arity == 2:
if _is_bitwise_op(node):
r1, r2 = pipe([node, ctx],
juxt([
comp(attrgetter("operands"), first),
comp(
repeat,
flip(
merge,
dict(lhs=False,
thint=_THint.logic,
lhint=None)), second),
]), R.apply(zip), map(R.apply(_printexpr)))
expr = pipe([r1, _get_op(node), r2], " ".join)
if thint == _THint.un_signed:
return _unsigned(expr)
elif thint == _THint.integer:
return _fn_call("to_integer", expr)
else:
return expr
elif _is_comp_op(node):
if pipe(node.operands, R.all_satisfy(comp(R.equals(1), len))):
r1, r2 = pipe([node, ctx],
juxt([
comp(attrgetter("operands"), first),
comp(
repeat,
flip(
merge,
dict(lhs=False,
thint=_THint.logic,
lhint=None)), second),
]), R.apply(zip), R.map(R.apply(_printexpr)))
else:
r1, r2 = pipe(
[node, ctx],
juxt([
comp(attrgetter("operands"), first),
comp(repeat, second)
]), R.apply(zip),
map(
juxt([
first,
comp(
R.apply(merge),
juxt([
second,
R.always(dict(lhs=False, lhint=None)),
R.if_else(
comp(R.isinstance(Constant), first),
R.always(dict(thint=_THint.integer)),
R.always(dict(thint=_THint.un_signed)))
]))
])), map(R.apply(_printexpr)))
if thint == _THint.logic:
return _fn_call(pipe(node, _get_op, "\\?{}\\".format), r1, r2)
else:
return pipe([r1, _get_op(node), r2], " ".join)
elif _is_shift_op(node):
r1, r2 = pipe(
[node, ctx],
juxt([
comp(attrgetter("operands"), first),
comp(repeat, second)
]), R.apply(zip),
map(
juxt([
first,
comp(
R.apply(merge),
juxt([
second,
R.always(dict(lhs=False, lhint=None)),
R.if_else(
comp(R.isinstance(Constant), first),
R.always(dict(thint=_THint.integer)),
R.always(dict(thint=_THint.un_signed)))
]))
])), map(R.apply(_printexpr)))
expr = _fn_call(_shift_op[node.op], r1, r2)
if thint == _THint.integer:
return _fn_call("to_integer", expr)
elif thint == _THint.logic:
return _std_logic_vector(expr)
else:
return expr
elif _is_arith_op(node):
r1, r2 = pipe(
node.operands,
map(lambda x: _printexpr(
x,
merge(
ctx,
dict(lhs=False,
thint=_THint.integer if R.isinstance(Constant, x)
else _THint.un_signed,
lhint=None)))))
expr = pipe([r1, _arith_op_map[node.op], r2], " ".join)
if thint == _THint.integer:
return _fn_call("to_integer", expr)
elif thint == _THint.logic:
return _std_logic_vector(expr)
else:
return expr
raise TypeError("unkown operator: {}, arity: {}".format(node, arity))
def __init__(self, bus, nbits_source=None, fifo_depth=None):
ar, r = operator.attrgetter("ar", "r")(bus)
dw = bus.data_width
alignment_bits = bits_for(dw // 8) - 1
if nbits_source:
if nbits_source % 8:
raise ValueError("nbits_source must be a multiple of 8")
if nbits_source > dw:
raise ValueError("nbits_source must be <= bus.data_width")
nbits_source = nbits_source or dw
counter_bits = bits_for(
(2**len(bus.ar.addr) - 1) // (nbits_source // 8))
self.sink = stream.Endpoint(
pipe(rec_layout(ar, {"addr"}),
juxt([
identity,
R.always([("n", counter_bits)]),
]), concat, list))
self.source = stream.Endpoint([("data", nbits_source)])
###
sink_consume = Signal()
self.comb += sink_consume.eq(self.sink.stb & self.sink.ack)
remaining = Countdown(counter_bits)
self.submodules += remaining
self.comb += [
remaining.count_w.eq(self.sink.n),
remaining.we.eq(sink_consume),
remaining.ce.eq(self.source.stb & self.source.ack),
]
eop_consumed = Signal()
self.sync += [
If(
sink_consume,
eop_consumed.eq(0),
).Elif(self.source.stb & self.source.ack & self.source.eop,
eop_consumed.eq(1))
]
converter = stream.Converter(dw, nbits_source)
self.submodules += converter
self.comb += [
converter.source.ack.eq(self.source.ack | eop_consumed),
self.source.stb.eq(converter.source.stb & ~eop_consumed),
self.source.eop.eq(remaining.done),
self.source.data.eq(converter.source.data),
]
fifo_depth = min(fifo_depth or BURST_LENGTH, BURST_LENGTH)
if fifo_depth % (dw // 8):
raise ValueError("fifo_depth shall be a multiple of wordsize")
rfifo = stream.SyncFIFO(rec_layout(r, {"data"}), depth=fifo_depth)
self.submodules += rfifo
self.comb += rfifo.source.connect(converter.sink)
burst_done = Signal()
self.sync += burst_done.eq(r.valid & r.ready & r.last)
# ar channel
ar_acked = Signal(reset=1)
sink_acked = Signal()
self.sync += [
If(sink_consume, sink_acked.eq(1)).Elif(remaining.done,
sink_acked.eq(0))
]
self.sync += [
If(
sink_consume,
ar_acked.eq(0),
ar.addr[alignment_bits:].eq(self.sink.addr[alignment_bits:]),
).Else(
If(burst_done & ~remaining.done, ar_acked.eq(0),
ar.addr.eq(ar.addr + fifo_depth * dw // 8)),
If(ar.valid & ar.ready, ar_acked.eq(1))),
]
self.comb += [
self.sink.ack.eq(~sink_acked & remaining.done),
ar.len.eq(fifo_depth - 1),
ar.size.eq(burst_size(dw // 8)),
ar.burst.eq(Burst.incr.value),
# ensure FIFO is clear to not stall the bus
ar.valid.eq(~ar_acked & ~rfifo.source.stb)
]
# r channel
self.comb += [
remaining.ce.eq(rfifo.sink.stb & rfifo.sink.ack),
rfifo.sink.data.eq(r.data),
rfifo.sink.stb.eq(r.valid),
r.ready.eq(rfifo.sink.ack),
]