Exemplo n.º 1
0
Arquivo: vhdl.py Projeto: peteut/migen
def _printnode_assign(node, ctx):
    at = get("at", ctx)
    if R.isinstance(Cat, node.l):
        return pipe(
            node.l.l,
            reversed,
            map(juxt([identity, len])),
            list,
            juxt([identity, comp(sum, map(second))]),
            juxt([first,
                  comp(reduce(partial(accumulate, sub)),
                       juxt([comp(map(second), first),
                             second]))]),
            R.apply(zip),
            map(lambda x: _printnode(
                x[0][0].eq(node.r[x[1] - x[0][1]: x[1]]), ctx)),
            ";\n".join)

    lhs = _printexpr(node.l, merge(ctx,
                                   dict(lhs=True,
                                        thint=_THint.logic,
                                        lhint=None)))
    rhs = _printexpr(node.r, merge(ctx,
                                   dict(
                                       lhs=False,
                                       thint=_THint.logic,
                                       lhint=len(node.l)
                                       if R.isinstance(Constant, node.r) or
                                       len(node.l) > len(node.r)
                                       else None)))

    return pipe([lhs, ":=" if at == _AT_BLOCKING else "<=", rhs], " ".join)
Exemplo n.º 2
0
Arquivo: vhdl.py Projeto: peteut/migen
def _printnode_assign(node, ctx):
    at = get("at", ctx)
    if R.isinstance(Cat, node.l):
        return pipe(
            node.l.l, reversed, map(juxt([identity, len])), list,
            juxt([identity, comp(sum, map(second))]),
            juxt([
                first,
                comp(reduce(partial(accumulate, sub)),
                     juxt([comp(map(second), first), second]))
            ]), R.apply(zip),
            map(lambda x: _printnode(x[0][0].eq(node.r[x[1] - x[0][1]:x[1]]),
                                     ctx)), ";\n".join)

    lhs = _printexpr(
        node.l, merge(ctx, dict(lhs=True, thint=_THint.logic, lhint=None)))
    rhs = _printexpr(
        node.r,
        merge(
            ctx,
            dict(lhs=False,
                 thint=_THint.logic,
                 lhint=len(node.l) if R.isinstance(Constant, node.r)
                 or len(node.l) > len(node.r) else None)))

    return pipe([lhs, ":=" if at == _AT_BLOCKING else "<=", rhs], " ".join)
Exemplo n.º 3
0
def connect_interface(interface, ps_m=True):
    return pipe(
        interface.iter_flat(),
        map(
            juxt([
                comp(
                    R.apply(operator.concat),
                    juxt([
                        comp(
                            comp(
                                flip(get)(dict([
                                    (DIR_M_TO_S, "o_" if ps_m else "i_"),
                                    (DIR_S_TO_M, "i_" if ps_m else "o_"),
                                    (DIR_NONE, "io_")
                                ])), get(-1))),
                        comp(operator.methodcaller("upper"), sig_name, first),
                    ])), first
            ])), dict)
Exemplo n.º 4
0
 def like(other, name=None):
     return pipe(
         other, operator.attrgetter("data_width", "addr_width", "id_width"),
         R.apply(partial(Interface, name=name)))
Exemplo n.º 5
0
                                maybe_none_resolver)

data = cata(tagfn(me.find_all('tr')), at3)
data2 = cata(tagfn(me.find_all('td')), data)
data_texts = cata(tagfn(mn.get_text()), data2)
data3 = cata(tagfn(mn.find('a')), data2)
data_titles = cata(tagfn(mn.get('title')), data3)
data_links = cata(tagfn(mn.get('href')), data3)
#data5 = cata(tagfn(maybe_none_resolver),data4)

uw_titles = cata(lambda x: x.value
                 if isinstance(x, md.Maybe) else x, data_titles)
uw_texts = cata(lambda x: x.value
                if isinstance(x, md.Maybe) else x, data_texts)
w_titles = cata(
    r.if_else(r.isinstance(list), r.identity,
              r.compose(md.First, maybe_none_resolver)), uw_titles)
w_texts = cata(r.if_else(r.isinstance(list), r.identity, maybe_none_resolver),
               uw_texts)

out = cata(
    r.if_else(
        lambda x: True
        if isinstance(x, tuple) and isinstance(x[0], md.Container) else False,
        r.apply(r.add), r.identity), (w_titles, w_texts))

out2 = cata(
    r.if_else(r.isinstance(md.First), lambda x: x.value.value, r.identity),
    out)
out3 = cata(r.if_else(r.isinstance(md.Just), lambda x: x.value, r.identity),
            out2)
Exemplo n.º 6
0
Arquivo: mn.py Projeto: flintc/sandbox
def cata2(f, xy):
    # First, we recurse inside all the values in data
    cata_on_f = lambda xy: cata2(r.apply(f), xy)
    recursed = fmap(cata_on_f, data)
    # Then, we apply f to the result
    return f(recursed)
Exemplo n.º 7
0
import operator
import toolz.curried as toolz
import pyramda as R

reg_typename = "{}_reg_t".format

rin_name = "{}_rin".format

r_name = "{}_r".format

v_name = "{}_v".format

architecture_id = "two_process_{}".format

indent = R.curry_n(
    2,
    toolz.comp(
        "\n".join,
        R.apply(map),
        R.unapply(toolz.juxt([
            toolz.comp(R.add, R.multiply("    "), toolz.first),
            toolz.comp(operator.methodcaller("split", "\n"), toolz.second)]))))
Exemplo n.º 8
0
import operator
import toolz.curried as toolz
import pyramda as R

reg_typename = "{}_reg_t".format

rin_name = "{}_rin".format

r_name = "{}_r".format

v_name = "{}_v".format

architecture_id = "two_process_{}".format

indent = R.curry_n(
    2,
    toolz.comp(
        "\n".join, R.apply(map),
        R.unapply(
            toolz.juxt([
                toolz.comp(R.add, R.multiply("    "), toolz.first),
                toolz.comp(operator.methodcaller("split", "\n"), toolz.second)
            ]))))
Exemplo n.º 9
0
Arquivo: vhdl.py Projeto: peteut/migen
def _printexpr_operator(node, ctx):
    thint = get("thint", ctx)
    arity = len(node.operands)
    if arity == 1:
        r1 = _printexpr(node.operands[0],
                        merge(ctx, dict(lhs=False,
                                        thint=_THint.logic,
                                        lhint=None)))
        if node.op == "-":
            expr = "(-{})".format(_signed(r1))
            if thint == _THint.un_signed:
                return expr
            elif thint == _THint.integer:
                return _to_integer(expr)
            elif thint == _THint.logic:
                return _std_logic_vector(expr)
            else:
                return expr
        else:
            expr = "{} {}".format(_get_op(node), r1)
            if thint == _THint.un_signed:
                return _unsigned(expr)
            elif thint == _THint.integer:
                return _fn_call("to_integer", _unsigned(expr))
            elif thint == _THint.boolean:
                return _fn_call("\\??\\", expr)
            else:
                return "({})".format(expr)
    elif arity == 2:
        if _is_bitwise_op(node):
            r1, r2 = pipe(
                [node, ctx],
                juxt([
                    comp(attrgetter("operands"), first),
                    comp(repeat, flip(merge, dict(lhs=False,
                                                  thint=_THint.logic,
                                                  lhint=None)), second),
                ]), R.apply(zip), map(R.apply(_printexpr)))
            expr = pipe([r1, _get_op(node), r2], " ".join)
            if thint == _THint.un_signed:
                return _unsigned(expr)
            elif thint == _THint.integer:
                return _fn_call("to_integer", expr)
            else:
                return expr
        elif _is_comp_op(node):
            if pipe(node.operands, R.all_satisfy(comp(R.equals(1), len))):
                r1, r2 = pipe(
                    [node, ctx],
                    juxt([
                        comp(attrgetter("operands"), first),
                        comp(repeat, flip(merge, dict(lhs=False,
                                                      thint=_THint.logic,
                                                      lhint=None)), second),
                    ]), R.apply(zip), R.map(R.apply(_printexpr)))
            else:
                r1, r2 = pipe(
                    [node, ctx],
                    juxt([
                        comp(attrgetter("operands"), first),
                        comp(repeat, second)]), R.apply(zip),
                    map(juxt([
                        first,
                        comp(
                            R.apply(merge),
                            juxt([
                                second,
                                R.always(dict(lhs=False, lhint=None)),
                                R.if_else(
                                    comp(R.isinstance(Constant), first),
                                    R.always(dict(thint=_THint.integer)),
                                    R.always(dict(thint=_THint.un_signed)))
                            ]))])),
                    map(R.apply(_printexpr)))
            if thint == _THint.logic:
                return _fn_call(pipe(node, _get_op, "\\?{}\\".format), r1, r2)
            else:
                return pipe([r1, _get_op(node), r2], " ".join)
        elif _is_shift_op(node):
            r1, r2 = pipe(
                [node, ctx],
                juxt([
                    comp(attrgetter("operands"), first),
                    comp(repeat, second)]), R.apply(zip),
                map(juxt([
                    first,
                    comp(
                        R.apply(merge),
                        juxt([
                            second,
                            R.always(dict(lhs=False, lhint=None)),
                            R.if_else(
                                comp(R.isinstance(Constant), first),
                                R.always(dict(thint=_THint.integer)),
                                R.always(dict(thint=_THint.un_signed)))
                        ]))])),
                map(R.apply(_printexpr)))
            expr = _fn_call(_shift_op[node.op], r1, r2)
            if thint == _THint.integer:
                return _fn_call("to_integer", expr)
            elif thint == _THint.logic:
                return _std_logic_vector(expr)
            else:
                return expr
        elif _is_arith_op(node):
            r1, r2 = pipe(
                node.operands,
                map(lambda x:
                    _printexpr(x,
                               merge(ctx,
                                     dict(lhs=False,
                                          thint=_THint.integer
                                          if R.isinstance(Constant, x)
                                          else _THint.un_signed,
                                          lhint=None)))))
            expr = pipe([r1, _arith_op_map[node.op], r2], " ".join)
            if thint == _THint.integer:
                return _fn_call("to_integer", expr)
            elif thint == _THint.logic:
                return _std_logic_vector(expr)
            else:
                return expr

    raise TypeError("unkown operator: {}, arity: {}".format(node, arity))
Exemplo n.º 10
0
Arquivo: vhdl.py Projeto: peteut/migen
    "restrict_guarantee", "return", "rol", "ror", "select", "sequence",
    "severity", "shared", "signal", "sla", "sll", "sra", "srl", "strong",
    "subtype", "then", "to", "transport", "type", "unaffected", "units",
    "until", "use", "variable", "vmode", "vprop", "vunit", "wait", "when",
    "while", "whith", "xnor", "xor"}


_get_sigtype = R.if_else(
    comp(R.equals(1), len),
    R.always("std_ulogic"),
    comp("std_logic_vector({} downto 0)".format, R.dec, len))

_sort_by_hash = partial(sorted, key=hash)

_sigs = comp(
    R.apply(or_),
    juxt([
        list_signals,
        partial(list_special_ios, ins=True, outs=True, inouts=True)]))

_inouts = partial(list_special_ios, ins=False, outs=False, inouts=True)

_targets = comp(
    R.apply(or_),
    juxt([
        list_targets,
        partial(list_special_ios, ins=False, outs=True, inouts=True)]))

lookup = TemplateLookup(directories=[
    os.path.abspath(os.path.join(os.path.dirname(__file__), "./templates"))])
Exemplo n.º 11
0
    def __init__(self,
                 pads=SimpleNamespace(ps=None,
                                      ddr=None,
                                      enet0=None,
                                      enet1=None),
                 **kwargs):
        pads.ps = pads.ps or ps_rec()
        pads.ddr = pads.ddr or ddr_rec()

        self.m_axi_gp0 = Interface(id_width=12)
        self.m_axi_gp1 = Interface(id_width=12)
        self.s_axi_gp0 = Interface(id_width=6)
        self.s_axi_gp1 = Interface(id_width=6)
        self.s_axi_acp = Interface(data_width=64, id_width=3)
        self.s_axi_acp_user = acp_user_rec(name="s_axi_acp")
        self.s_axi_hp0 = Interface(data_width=64, addr_width=32, id_width=6)
        self.s_axi_hp0_fifo = hp_fifo_rec(name="s_axi_hp0")
        self.s_axi_hp1 = Interface(data_width=64, addr_width=32, id_width=6)
        self.s_axi_hp1_fifo = hp_fifo_rec(name="s_axi_hp1")
        self.s_axi_hp2 = Interface(data_width=64, addr_width=32, id_width=6)
        self.s_axi_hp2_fifo = hp_fifo_rec(name="s_axi_hp2")
        self.s_axi_hp3 = Interface(data_width=64, addr_width=32, id_width=6)
        self.s_axi_hp3_fifo = hp_fifo_rec(name="s_axi_hp3")

        self.ttc0 = ttc_rec()
        self.ttc1 = ttc_rec()
        self.wdt = wdt_rec()
        self.spi0 = spio_rec()
        self.spi1 = spio_rec()
        self.i2c0 = i2c_rec()
        self.i2c1 = i2c_rec()
        self.can0 = can_rec()
        self.can1 = can_rec()
        self.uart0 = uart_rec()
        self.uart1 = uart_rec()
        self.sdio0 = sdio_rec()
        self.sdio1 = sdio_rec()
        self.gpio = gpio_rec()
        self.usb0 = usb_rec()
        self.usb1 = usb_rec()
        self.sram = sram_rec()
        self.fpga_idle_n = Signal()
        self.event = event_rec()
        self.ddr_arb = Signal(4)
        self.mio = Signal(54)

        self.clock_domains.cd_sys = ClockDomain()
        self.clock_domains.cd_por = ClockDomain(reset_less=True)

        self.dma0 = dmac_bus.Interface(name="dma0")
        self.dma1 = dmac_bus.Interface(name="dma1")
        self.dma2 = dmac_bus.Interface(name="dma2")
        self.dma3 = dmac_bus.Interface(name="dma3")

        self.spi = Record([
            ("can1", 1),
            ("uart1", 1),
            ("spi1", 1),
            ("i2c1", 1),
            ("sdio1", 1),
            ("enet1_wake", 1),
            ("enet1", 1),
            ("usb1", 1),
            ("can0", 1),
            ("uart0", 1),
            ("spi0", 1),
            ("i2c0", 1),
            ("sdio0", 1),
            ("enet0_wake", 1),
            ("enet0", 1),
            ("usb0", 1),
            ("gpio", 1),
            ("cti", 1),
            ("qspi", 1),
            ("smc", 1),
            ("dmac", 8),
            ("dmac_abort", 1),
        ])
        self.interrupt = Signal(16)
        self.core = Record([
            ("core0", [("nirq", 1), ("nfiq", 1)]),
            ("core1", [("nirq", 1), ("nfiq", 1)]),
        ])
        self.trace = trace_rec()
        self.pjtag = pjtag_rec()

        ###

        s_axi_gp0_shim = Interface.like(self.s_axi_gp0, "s_axi_gp0")
        s_axi_gp1_shim = Interface.like(self.s_axi_gp1, "s_axi_gp1")
        wrshim_s_axi_gp0 = wrshim.AxiWrshim()
        wrshim_s_axi_gp1 = wrshim.AxiWrshim()
        m_axi_gp_global = [
            axi_global_rec(name="m_axi_gp{}".format(i)) for i in range(2)
        ]
        self.comb += [i.aclk.eq(ClockSignal()) for i in m_axi_gp_global]
        s_axi_gp_global = [
            axi_global_rec(name="s_axi_gp{}".format(i)) for i in range(2)
        ]
        self.comb += [i.aclk.eq(ClockSignal()) for i in s_axi_gp_global]
        s_axi_acp_global = axi_global_rec(name="s_axi_acp")
        self.comb += [s_axi_acp_global.aclk.eq(ClockSignal())]
        s_axi_hp_global = [
            axi_global_rec(name="s_axi_hp{}".format(i)) for i in range(4)
        ]
        self.comb += [i.aclk.eq(ClockSignal()) for i in s_axi_hp_global]
        dma_global = [dma_global_rec(name="dma{}".format(i)) for i in range(4)]
        [
            setattr(self, "dma{}_rst_n".format(i), rec.rst_n)
            for i, rec in enumerate(dma_global)
        ]
        self.comb += [i.aclk.eq(ClockSignal()) for i in dma_global]

        self.submodules.enet0 = ClockDomainsRenamer(
            dict(eth_rx="enet0_rx",
                 eth_tx="enet0_tx"))(ENET(getattr(pads, "enet0", None)))
        self.submodules.enet1 = ClockDomainsRenamer(
            dict(eth_rx="enet1_rx",
                 eth_tx="enet1_tx"))(ENET(getattr(pads, "enet1", None)))

        ddr_buf, ps_buf = ddr_rec(name="ddr"), ps_rec(name="ps")
        mio_buf = Signal(len(self.mio))

        pads_ddr_v = Signal(len(pads.ddr))
        ddr_buf_v = Signal(len(ddr_buf))
        self.comb += [
            pads_ddr_v.eq(pads.ddr.raw_bits()),
        ]
        self.specials += [
            bibuf([pads_ddr_v[i], ddr_buf_v[i]])
            for i in range(len(pads_ddr_v))
        ]
        self.specials += [
            bibuf([pads.ps.clk, ps_buf.clk]),
            bibuf([pads.ps.por_b, ps_buf.por_b]),
            bibuf([pads.ps.srst_b, ps_buf.srst_b])
        ]
        self.specials += [
            bibuf([self.mio[i], mio_buf[i]]) for i in range(len(self.mio))
        ]

        self.submodules += [
            wrshim_s_axi_gp0,
            InterconnectPointToPoint(self.s_axi_gp0, s_axi_gp0_shim),
            wrshim_s_axi_gp1,
            InterconnectPointToPoint(self.s_axi_gp1, s_axi_gp1_shim),
        ]

        self.fclk = fclk_rec()
        # fclk.reset_n considered async
        self.specials += [
            AsyncResetSynchronizer(self.cd_sys, ~self.fclk.reset_n[0]),
            bufg([self.fclk.clk[0], ClockSignal()]),
        ]

        self.comb += self.fclk.clktrig_n.eq(0)
        ftmd = ftmd_rec()
        ftmt = ftmt_rec()
        irq = irq_rec()
        self.comb += [
            irq.f2p[:16].eq(self.interrupt),
            irq.f2p[16:20].eq(
                Cat(self.core.core0.nirq, self.core.core1.nirq,
                    self.core.core0.nfiq, self.core.core1.nfiq)),
            self.spi.raw_bits().eq(irq.p2f),
        ]
        ps7_attrs = pipe(
            [
                connect_interface(s_axi_gp_global[0]),
                connect_s_axi(s_axi_gp0_shim),
                connect_interface(s_axi_gp_global[1]),
                connect_s_axi(s_axi_gp1_shim),
                connect_interface(m_axi_gp_global[0]),
                connect_m_axi(self.m_axi_gp0),
                connect_interface(m_axi_gp_global[1]),
                connect_m_axi(self.m_axi_gp1),
                connect_interface(s_axi_acp_global),
                connect_s_axi(self.s_axi_acp),
                connect_interface(self.s_axi_acp_user),
                connect_interface(s_axi_hp_global[0]),
                connect_interface(self.s_axi_hp0, False),
                connect_interface(self.s_axi_hp0_fifo),
                connect_interface(s_axi_hp_global[1]),
                connect_interface(self.s_axi_hp1, False),
                connect_interface(self.s_axi_hp1_fifo),
                connect_interface(s_axi_hp_global[2]),
                connect_interface(self.s_axi_hp2, False),
                connect_interface(self.s_axi_hp2_fifo),
                connect_interface(s_axi_hp_global[3]),
                connect_interface(self.s_axi_hp3, False),
                connect_interface(self.s_axi_hp3_fifo),
                connect_interface(ddr_buf),
                dict(io_MIO=mio_buf),
                connect_interface(self.ttc0),
                connect_interface(self.ttc1),
                connect_interface(self.wdt),
                connect_interface(self.spi0),
                connect_interface(self.spi1),
                connect_interface(self.i2c0),
                connect_interface(self.i2c1),
                connect_interface(self.can0),
                connect_interface(self.can1),
                connect_interface(self.uart0),
                connect_interface(self.uart1),
                connect_interface(self.sdio0),
                connect_interface(self.sdio1),
                connect_interface(self.gpio),
                keymap(str_replace("TRACE", "EMIOTRACE"),
                       connect_interface(self.trace)),
                connect_interface(self.pjtag),
                connect_interface(self.usb0),
                connect_interface(self.usb1),
                connect_interface(self.sram),
                connect_interface(self.fclk),
                dict(i_FPGAIDLEN=self.fpga_idle_n),
                connect_interface(self.event),
                dict(i_DDRARB=self.ddr_arb),
                connect_interface(ftmd),
                connect_interface(ftmt),
                connect_interface(dma_global[0]),
                connect_interface(self.dma0),
                connect_interface(dma_global[1]),
                connect_interface(self.dma1),
                connect_interface(dma_global[2]),
                connect_interface(self.dma2),
                connect_interface(dma_global[3]),
                connect_interface(self.dma3),
                connect_interface(irq),
                dict(io_PSPORB=ps_buf.por_b,
                     io_PSSRSTB=ps_buf.srst_b,
                     io_PSCLK=ps_buf.clk),
                keymap(str_replace("ENET", "EMIOENET0"),
                       connect_interface(self.enet0.enet)),
                keymap(str_replace("ENET", "EMIOENET1"),
                       connect_interface(self.enet1.enet)),
            ],
            R.apply(merge),
            keymap(str_replace("TTC", "EMIOTTC")),
            keymap(str_replace("WDT", "EMIOWDT")),
            keymap(str_replace("SPI", "EMIOSPI")),
            keymap(str_replace("I2C", "EMIOI2C")),
            keymap(str_replace("CAN", "EMIOCAN")),
            keymap(str_replace("UART", "EMIOUART")),
            keymap(str_replace("SDIO", "EMIOSDIO")),
            keymap(str_replace("GPIO", "EMIOGPIO")),
            keymap(str_replace("PJTAG", "EMIOPJTAG")),
            keymap(str_replace("USB", "EMIOUSB")),
            keymap(str_replace("SRAM", "EMIOSRAM")),
            keymap(str_replace("DDRDRSTN", "DDRDRSTB")),
            keymap(str_replace("DDRWEN", "DDRWEB")),
            keymap(str_replace("DDRRASN", "DDRRASB")),
            keymap(str_replace("DDRCASN", "DDRCASB")),
            keymap(str_replace("DDRCSN", "DDRCSB")),
            keymap(str_replace("EMIOSPI0SSTN", "EMIOSPI0SSNTN")),
            keymap(str_replace("EMIOSPI1SSTN", "EMIOSPI1SSNTN")),
            keymap(str_replace("EMIOSPI0MTN", "EMIOSPI0MOTN")),
            keymap(str_replace("EMIOSPI1MTN", "EMIOSPI1MOTN")),
            keymap(str_replace("EVENTO", "EVENTEVENTO")),
            keymap(str_replace("EVENTI", "EVENTEVENTI")),
        )
        self.specials += Instance("PS7", **ps7_attrs)
Exemplo n.º 12
0
                    R.apply(operator.concat),
                    juxt([
                        comp(
                            comp(
                                flip(get)(dict([
                                    (DIR_M_TO_S, "o_" if ps_m else "i_"),
                                    (DIR_S_TO_M, "i_" if ps_m else "o_"),
                                    (DIR_NONE, "io_")
                                ])), get(-1))),
                        comp(operator.methodcaller("upper"), sig_name, first),
                    ])), first
            ])), dict)


fix_arsize = comp(
    R.apply(update_in),
    juxt([
        identity,
        comp(list, filter(flip(str.endswith, "ARSIZE"))),
        R.always(get(slice(-1))),
    ]))

fix_awsize = comp(
    R.apply(update_in),
    juxt([
        identity,
        comp(list, filter(flip(str.endswith, "AWSIZE"))),
        R.always(get(slice(-1))),
    ]))

Exemplo n.º 13
0
Arquivo: vhdl.py Projeto: peteut/migen
def _printexpr_operator(node, ctx):
    thint = get("thint", ctx)
    arity = len(node.operands)
    if arity == 1:
        r1 = _printexpr(
            node.operands[0],
            merge(ctx, dict(lhs=False, thint=_THint.logic, lhint=None)))
        if node.op == "-":
            expr = "(-{})".format(_signed(r1))
            if thint == _THint.un_signed:
                return expr
            elif thint == _THint.integer:
                return _to_integer(expr)
            elif thint == _THint.logic:
                return _std_logic_vector(expr)
            else:
                return expr
        else:
            expr = "{} {}".format(_get_op(node), r1)
            if thint == _THint.un_signed:
                return _unsigned(expr)
            elif thint == _THint.integer:
                return _fn_call("to_integer", _unsigned(expr))
            elif thint == _THint.boolean:
                return _fn_call("\\??\\", expr)
            else:
                return "({})".format(expr)
    elif arity == 2:
        if _is_bitwise_op(node):
            r1, r2 = pipe([node, ctx],
                          juxt([
                              comp(attrgetter("operands"), first),
                              comp(
                                  repeat,
                                  flip(
                                      merge,
                                      dict(lhs=False,
                                           thint=_THint.logic,
                                           lhint=None)), second),
                          ]), R.apply(zip), map(R.apply(_printexpr)))
            expr = pipe([r1, _get_op(node), r2], " ".join)
            if thint == _THint.un_signed:
                return _unsigned(expr)
            elif thint == _THint.integer:
                return _fn_call("to_integer", expr)
            else:
                return expr
        elif _is_comp_op(node):
            if pipe(node.operands, R.all_satisfy(comp(R.equals(1), len))):
                r1, r2 = pipe([node, ctx],
                              juxt([
                                  comp(attrgetter("operands"), first),
                                  comp(
                                      repeat,
                                      flip(
                                          merge,
                                          dict(lhs=False,
                                               thint=_THint.logic,
                                               lhint=None)), second),
                              ]), R.apply(zip), R.map(R.apply(_printexpr)))
            else:
                r1, r2 = pipe(
                    [node, ctx],
                    juxt([
                        comp(attrgetter("operands"), first),
                        comp(repeat, second)
                    ]), R.apply(zip),
                    map(
                        juxt([
                            first,
                            comp(
                                R.apply(merge),
                                juxt([
                                    second,
                                    R.always(dict(lhs=False, lhint=None)),
                                    R.if_else(
                                        comp(R.isinstance(Constant), first),
                                        R.always(dict(thint=_THint.integer)),
                                        R.always(dict(thint=_THint.un_signed)))
                                ]))
                        ])), map(R.apply(_printexpr)))
            if thint == _THint.logic:
                return _fn_call(pipe(node, _get_op, "\\?{}\\".format), r1, r2)
            else:
                return pipe([r1, _get_op(node), r2], " ".join)
        elif _is_shift_op(node):
            r1, r2 = pipe(
                [node, ctx],
                juxt([
                    comp(attrgetter("operands"), first),
                    comp(repeat, second)
                ]), R.apply(zip),
                map(
                    juxt([
                        first,
                        comp(
                            R.apply(merge),
                            juxt([
                                second,
                                R.always(dict(lhs=False, lhint=None)),
                                R.if_else(
                                    comp(R.isinstance(Constant), first),
                                    R.always(dict(thint=_THint.integer)),
                                    R.always(dict(thint=_THint.un_signed)))
                            ]))
                    ])), map(R.apply(_printexpr)))
            expr = _fn_call(_shift_op[node.op], r1, r2)
            if thint == _THint.integer:
                return _fn_call("to_integer", expr)
            elif thint == _THint.logic:
                return _std_logic_vector(expr)
            else:
                return expr
        elif _is_arith_op(node):
            r1, r2 = pipe(
                node.operands,
                map(lambda x: _printexpr(
                    x,
                    merge(
                        ctx,
                        dict(lhs=False,
                             thint=_THint.integer if R.isinstance(Constant, x)
                             else _THint.un_signed,
                             lhint=None)))))
            expr = pipe([r1, _arith_op_map[node.op], r2], " ".join)
            if thint == _THint.integer:
                return _fn_call("to_integer", expr)
            elif thint == _THint.logic:
                return _std_logic_vector(expr)
            else:
                return expr

    raise TypeError("unkown operator: {}, arity: {}".format(node, arity))
Exemplo n.º 14
0
Arquivo: vhdl.py Projeto: peteut/migen
    "range", "record", "register", "reject", "release", "rem", "report",
    "restruct", "restrict_guarantee", "return", "rol", "ror", "select",
    "sequence", "severity", "shared", "signal", "sla", "sll", "sra", "srl",
    "strong", "subtype", "then", "to", "transport", "type", "unaffected",
    "units", "until", "use", "variable", "vmode", "vprop", "vunit", "wait",
    "when", "while", "whith", "xnor", "xor"
}

_get_sigtype = R.if_else(
    comp(R.equals(1), len), R.always("std_ulogic"),
    comp("std_logic_vector({} downto 0)".format, R.dec, len))

_sort_by_hash = partial(sorted, key=hash)

_sigs = comp(
    R.apply(or_),
    juxt([
        list_signals,
        partial(list_special_ios, ins=True, outs=True, inouts=True)
    ]))

_inouts = partial(list_special_ios, ins=False, outs=False, inouts=True)

_targets = comp(
    R.apply(or_),
    juxt([
        list_targets,
        partial(list_special_ios, ins=False, outs=True, inouts=True)
    ]))

lookup = TemplateLookup(directories=[
Exemplo n.º 15
0
 def __call__(self,*x):
     return r.apply(self.value)(x)