def test_edge_case_1(self):
in_1 = pyrtl.Input(10)
in_2 = pyrtl.Input(9)
fake_loop_wire = pyrtl.WireVector(1)
comp_wire = pyrtl.corecircuits.concat(in_2[0:4], fake_loop_wire, in_2[4:9])
r_wire = in_1 & comp_wire
fake_loop_wire <<= r_wire[3]
out = pyrtl.Output(10)
out <<= fake_loop_wire
# Yes, because we only check loops on a net level, this will still be
# a loop pre synth
self.assertNotEqual(pyrtl.find_loop(), None)
pyrtl.synthesize()
# Because synth separates the individual wires, it also resolves the loop
self.assertEqual(pyrtl.find_loop(), None)
pyrtl.optimize()
self.assertEqual(pyrtl.find_loop(), None)
def test_edge_case_1(self):
in_1 = pyrtl.Input(10)
in_2 = pyrtl.Input(9)
fake_loop_wire = pyrtl.WireVector(1)
comp_wire = pyrtl.concat(in_2[0:4], fake_loop_wire, in_2[4:9])
r_wire = in_1 & comp_wire
fake_loop_wire <<= r_wire[3]
out = pyrtl.Output(10)
out <<= fake_loop_wire
# Yes, because we only check loops on a net level, this will still be
# a loop pre synth
self.assertNotEqual(pyrtl.find_loop(), None)
pyrtl.synthesize()
# Because synth separates the individual wires, it also resolves the loop
self.assertEqual(pyrtl.find_loop(), None)
pyrtl.optimize()
self.assertEqual(pyrtl.find_loop(), None)
def assert_has_loop(self):
self.assertNotEqual(pyrtl.find_loop(), None)
pyrtl.synthesize()
self.assertNotEqual(pyrtl.find_loop(), None)
pyrtl.optimize()
self.assertNotEqual(pyrtl.find_loop(), None)
def assert_has_loop(self):
self.assertNotEqual(pyrtl.find_loop(), None)
pyrtl.synthesize()
self.assertNotEqual(pyrtl.find_loop(), None)
pyrtl.optimize()
self.assertNotEqual(pyrtl.find_loop(), None)
