def test_check_testports(self):
"""
Check if checking for more than one test output per test port
per repeater block works.
"""
import pyhalbe
import pysthal
from pyhalco_common import Enum, left, top
import pyhalco_hicann_v2 as C
hicann = pysthal.HICANN()
# HRepeaterOnHICANN 0 and 2 are on different test ports
hicann.repeater[C.HRepeaterOnHICANN(Enum(0))].setOutput(left)
hicann.repeater[C.HRepeaterOnHICANN(Enum(2))].setOutput(left)
self.assertEqual(hicann.check(), "")
hicann.repeater.clearReapeater()
# HRepeaterOnHICANN 0 and 4 are on the same test port
hicann.repeater[C.HRepeaterOnHICANN(Enum(0))].setOutput(left)
hicann.repeater[C.HRepeaterOnHICANN(Enum(4))].setOutput(left)
self.assertNotEqual(hicann.check(), "")
hicann.repeater.clearReapeater()
# VRepeaterOnHICANN 0 and 2 are on the same test port
hicann.repeater[C.VRepeaterOnHICANN(Enum(0))].setOutput(top)
hicann.repeater[C.VRepeaterOnHICANN(Enum(2))].setOutput(top)
self.assertNotEqual(hicann.check(), "")
hicann.repeater.clearReapeater()
# VRepeaterOnHICANN 0 and 4 are on different test ports
hicann.repeater[C.VRepeaterOnHICANN(Enum(0))].setOutput(top)
hicann.repeater[C.VRepeaterOnHICANN(Enum(1))].setOutput(top)
self.assertEqual(hicann.check(), "")
hicann.repeater.clearReapeater()
def test_get_address(self):
"""
Tests getting the full 6-bit L1 address a synapse decodes
"""
import pyhalbe
import pysthal
from pyhalco_common import Enum, top, bottom
import pyhalco_hicann_v2 as C
h = pysthal.HICANN()
for syn_c in C.iter_all(C.SynapseOnHICANN):
drv_c = syn_c.toSynapseDriverOnHICANN()
row_config_c = syn_c.toSynapseRowOnHICANN().toRowOnSynapseDriver()
syn = h.synapses[syn_c]
drv = h.synapses[drv_c]
row_config = drv[row_config_c]
for addr in C.iter_all(pyhalbe.HICANN.L1Address):
syn.decoder = addr.getSynapseDecoderMask()
row_config.set_decoder(
top if syn_c.toSynapseColumnOnHICANN().toEnum().value() %
2 == 0 else bottom, addr.getDriverDecoderMask())
self.assertEqual(addr, h.synapses.get_address(syn_c))
def test_synapseswitch_exclusiveness(self):
"""
Check if checking of exclusiveness of synapse switch matrix works.
Warning: Does not check for all possible valid and invalid combinations.
"""
from pyhalbe.HICANN import SynapseSwitch
import pysthal
from pyhalco_common import iter_all, SideHorizontal
import pyhalco_hicann_v2 as C
hicann = pysthal.HICANN()
settings = pysthal.Settings.get()
# check per vline
for side in iter_all(SideHorizontal):
for vline in iter_all(C.VLineOnHICANN):
syn_drvs = [
syn_drv for syn_drv in vline.toSynapseDriverOnHICANN(side)
]
for syn_drv1, syn_drv2 in zip(syn_drvs, syn_drvs[1:]):
settings.synapse_switches.max_switches_per_column_per_side = 1
ssr1 = syn_drv1.toSynapseSwitchRowOnHICANN().line()
ssr2 = syn_drv2.toSynapseSwitchRowOnHICANN().line()
# one switch in vline -> ok
hicann.synapse_switches.set(vline, ssr1, True)
self.assertEqual(hicann.check(), "")
# two switches in vline -> invalid
hicann.synapse_switches.set(vline, ssr2, True)
self.assertNotEqual(hicann.check(), "")
settings.synapse_switches.max_switches_per_column_per_side = 2
self.assertEqual(hicann.check(), "")
hicann.clear_l1_switches()
# check per synapse switch row
for syn_drv in C.iter_all(C.SynapseDriverOnHICANN):
ssr = syn_drv.toSynapseSwitchRowOnHICANN()
vlines = [vl for vl in SynapseSwitch.get_lines(ssr)]
for vline1, vline2 in zip(vlines, vlines[1:]):
settings.synapse_switches.max_switches_per_row = 1
# one switch in switch row -> ok
hicann.synapse_switches.set(vline1, ssr.line(), True)
self.assertEqual(hicann.check(), "")
# two switches in switch row -> invalid
hicann.synapse_switches.set(vline2, ssr.line(), True)
self.assertNotEqual(hicann.check(), "")
settings.synapse_switches.max_switches_per_row = 2
self.assertEqual(hicann.check(), "")
hicann.clear_l1_switches()
def test_hicann_copy(self):
import copy
h = pysthal.HICANN()
self.assertFalse(h.has_wafer())
h2 = copy.deepcopy(h)
self.assertEqual(h, h2)
# change something to ensure that it's not a mere pointer copy
h.set_neuron_size(2)
self.assertNotEqual(h, h2)
def test_hicann_pickle(self):
import pickle
h = pysthal.HICANN()
self.assertFalse(h.has_wafer())
h_str = pickle.dumps(h)
h2 = pickle.loads(h_str)
self.assertEqual(h, h2)
# change something to ensure that it's not a mere pointer copy
h.set_neuron_size(2)
self.assertNotEqual(h, h2)
def test_configure(self):
route = L1Route()
hicann = HICANNOnWafer(X(6), Y(5))
route.append(hicann, HLineOnHICANN(48))
route.append(VLineOnHICANN(39))
wafer = pysthal.Wafer()
pyalone.configure(wafer, route)
self.assertEqual(1, len(wafer.getAllocatedHicannCoordinates()))
reference = pysthal.HICANN()
reference.crossbar_switches.set(VLineOnHICANN(39), HLineOnHICANN(48),
True)
self.assertEqual(reference, wafer[hicann])
def test_crossbar_exclusiveness(self):
"""
Check if checking of exclusiveness of the crossbar switch matrix works.
Warning: Does not check for all possible valid and invalid combinations.
"""
import pysthal
import pyhalco_hicann_v2 as C
hicann = pysthal.HICANN()
settings = pysthal.Settings.get()
# VLineOnHICANN::toHLineOnHICANN not implemented
vline_to_hline = defaultdict(list)
for hline in C.iter_all(C.HLineOnHICANN):
for vline1, vline2 in zip(hline.toVLineOnHICANN(),
hline.toVLineOnHICANN()[1:]):
vline_to_hline[vline1].append(hline)
settings.crossbar_switches.max_switches_per_row = 1
# one switch in hline
hicann.crossbar_switches.set(vline1, hline, True)
self.assertEqual(hicann.check(), "")
# two switches in hline
hicann.crossbar_switches.set(vline2, hline, True)
self.assertNotEqual(hicann.check(), "")
settings.crossbar_switches.max_switches_per_row = 2
self.assertEqual(hicann.check(), "")
hicann.clear_l1_switches()
for vline, hlines in vline_to_hline.items():
for hline1, hline2 in zip(hlines, hlines[1:]):
settings.crossbar_switches.max_switches_per_column = 1
# one switch in vline
hicann.crossbar_switches.set(vline, hline1, True)
self.assertEqual(hicann.check(), "")
# two switches in vline
hicann.crossbar_switches.set(vline, hline2, True)
self.assertNotEqual(hicann.check(), "")
settings.crossbar_switches.max_switches_per_column = 2
self.assertEqual(hicann.check(), "")
hicann.clear_l1_switches()
def test_SynapseProxies(self):
import pysthal
import pyhalbe
import pyhalco_hicann_v2
C = pyhalco_hicann_v2
hicann = pysthal.HICANN()
row_c = C.SynapseRowOnHICANN(40)
w = hicann.synapses[row_c].weights
w[0] = pyhalbe.HICANN.SynapseWeight(7)
self.assertEqual(hicann.synapses[row_c].weights[0],
pyhalbe.HICANN.SynapseWeight(7))
print(hicann.synapses[row_c].weights[0])
def test_synapse_access(self):
import pysthal
import numpy
import pyhalco_common
import pyhalco_hicann_v2
from pyhalbe import HICANN
d_patterns = {}
w_patterns = {}
hicann = pysthal.HICANN()
for row in pyhalco_common.iter_all(
pyhalco_hicann_v2.SynapseRowOnHICANN):
d_pattern = numpy.random.randint(0, 16, 256)
d_patterns[row] = d_pattern
hicann.synapses[row].decoders[:] = [
HICANN.SynapseDecoder(int(ii)) for ii in d_pattern
]
w_pattern = [
HICANN.SynapseWeight(int(ii))
for ii in numpy.random.randint(0, 16, 256)
]
w_patterns[row] = w_pattern
hicann.synapses[row].weights[:] = w_pattern
for drv in pyhalco_common.iter_all(
pyhalco_hicann_v2.SynapseDriverOnHICANN):
double_row = hicann.synapses.getDecoderDoubleRow(drv)
for x in (pyhalco_common.top, pyhalco_common.bottom):
row = pyhalco_hicann_v2.SynapseRowOnHICANN(drv, x)
data = numpy.array([int(ii) for ii in double_row[x.value()]])
if not numpy.all(data == d_patterns[row]):
err = "Missmatch in decoder values: {!s} != {!s} in {!s}".format(
data, d_patterns[row], row)
self.fail(err)
for syn in pyhalco_common.iter_all(pyhalco_hicann_v2.SynapseOnHICANN):
hicann.synapses[syn]
def test_neuronsize(self):
import pysthal
from pyhalco_common import iter_all, X
from pyhalco_hicann_v2 import NeuronOnHICANN, QuadOnHICANN
hicann = pysthal.HICANN()
sizes = [2**x for x in range(7)]
# There and back again
for size in sizes[:] + sizes[::-1]:
hicann.set_neuron_size(size)
hicann.check()
active = [
hicann.neurons[neuron].activate_firing()
for neuron in iter_all(NeuronOnHICANN)
]
self.assertEqual(active.count(True), 512 / size)
for quad in iter_all(QuadOnHICANN):
self.assertEqual(
hicann.neurons[quad].getVerticalInterconnect(X(0)),
(size > 1))
self.assertEqual(
hicann.neurons[quad].getVerticalInterconnect(X(1)),
(size > 1))
def test_find_neuron_in_analog_output(self):
"""
Check if find_neuron_in_analog_output works.
"""
import pysthal
from pyhalco_common import iter_all, X, Y
from pyhalco_hicann_v2 import NeuronOnHICANN, AnalogOnHICANN
hicann = pysthal.HICANN()
NeuronOnHICANN.__repr__ = NeuronOnHICANN.__str__
# Nothing active, this should throw
for analog in iter_all(AnalogOnHICANN):
with self.assertRaises(RuntimeError):
hicann.find_neuron_in_analog_output(analog)
# Enable 4 neurons, connected to different analog mux entries, but not
# the mux yet, this should throw
hicann.neurons[NeuronOnHICANN(X(0), Y(0))].enable_aout(True)
hicann.neurons[NeuronOnHICANN(X(1), Y(0))].enable_aout(True)
hicann.neurons[NeuronOnHICANN(X(0), Y(1))].enable_aout(True)
hicann.neurons[NeuronOnHICANN(X(1), Y(1))].enable_aout(True)
for analog in iter_all(AnalogOnHICANN):
with self.assertRaises(RuntimeError):
hicann.find_neuron_in_analog_output(analog)
# Now enable the mux for each of the neurons and check if the correct
# neuron was found
for analog in iter_all(AnalogOnHICANN):
hicann.analog.set_membrane_top_even(analog)
self.assertEqual(NeuronOnHICANN(X(0), Y(0)),
hicann.find_neuron_in_analog_output(analog))
hicann.analog.set_membrane_top_odd(analog)
self.assertEqual(NeuronOnHICANN(X(1), Y(0)),
hicann.find_neuron_in_analog_output(analog))
hicann.analog.set_membrane_bot_even(analog)
self.assertEqual(NeuronOnHICANN(X(0), Y(1)),
hicann.find_neuron_in_analog_output(analog))
hicann.analog.set_membrane_bot_odd(analog)
self.assertEqual(NeuronOnHICANN(X(1), Y(1)),
hicann.find_neuron_in_analog_output(analog))
hicann.analog.disable(analog)
# Now enable 4 more, each connected to different analog mux entries,
# now it should fail, because two neurons are connected
hicann.neurons[NeuronOnHICANN(X(30), Y(0))].enable_aout(True)
hicann.neurons[NeuronOnHICANN(X(41), Y(0))].enable_aout(True)
hicann.neurons[NeuronOnHICANN(X(10), Y(1))].enable_aout(True)
hicann.neurons[NeuronOnHICANN(X(255), Y(1))].enable_aout(True)
for analog in iter_all(AnalogOnHICANN):
hicann.analog.set_membrane_top_even(analog)
with self.assertRaises(RuntimeError):
hicann.find_neuron_in_analog_output(analog)
hicann.analog.set_membrane_top_odd(analog)
with self.assertRaises(RuntimeError):
hicann.find_neuron_in_analog_output(analog)
hicann.analog.set_membrane_bot_even(analog)
with self.assertRaises(RuntimeError):
hicann.find_neuron_in_analog_output(analog)
hicann.analog.set_membrane_bot_odd(analog)
with self.assertRaises(RuntimeError):
hicann.find_neuron_in_analog_output(analog)
hicann.analog.disable(analog)
# Now disable the first 4 neurons, and everything should be fine again
hicann.neurons[NeuronOnHICANN(X(0), Y(0))].enable_aout(False)
hicann.neurons[NeuronOnHICANN(X(1), Y(0))].enable_aout(False)
hicann.neurons[NeuronOnHICANN(X(0), Y(1))].enable_aout(False)
hicann.neurons[NeuronOnHICANN(X(1), Y(1))].enable_aout(False)
for analog in iter_all(AnalogOnHICANN):
hicann.analog.set_membrane_top_even(analog)
self.assertEqual(NeuronOnHICANN(X(30), Y(0)),
hicann.find_neuron_in_analog_output(analog))
hicann.analog.set_membrane_top_odd(analog)
self.assertEqual(NeuronOnHICANN(X(41), Y(0)),
hicann.find_neuron_in_analog_output(analog))
hicann.analog.set_membrane_bot_even(analog)
self.assertEqual(NeuronOnHICANN(X(10), Y(1)),
hicann.find_neuron_in_analog_output(analog))
hicann.analog.set_membrane_bot_odd(analog)
self.assertEqual(NeuronOnHICANN(X(255), Y(1)),
hicann.find_neuron_in_analog_output(analog))
hicann.analog.disable(analog)