def __init__(self, topmodule, terms, binddict,
resolved_terms, resolved_binddict, constlist):
VerilogDataflowMerge.__init__(self, topmodule, terms, binddict,
resolved_terms, resolved_binddict, constlist)
self.clock_name = 'CLK'
self.clock_edge = 'posedge'
self.reset_name = 'RST_X'
self.reset_edge = 'negedge'
def __init__(self, topmodule, terms, binddict, resolved_terms,
resolved_binddict, constlist):
VerilogDataflowMerge.__init__(self, topmodule, terms, binddict,
resolved_terms, resolved_binddict,
constlist)
self.clock_name = 'CLK'
self.clock_edge = 'posedge'
self.reset_name = 'RST_X'
self.reset_edge = 'negedge'
def __init__(self, topmodule, terms, binddict, resolved_terms,
resolved_binddict, constlist):
VerilogDataflowMerge.__init__(self, topmodule, terms, binddict,
resolved_terms, resolved_binddict,
constlist)
def __init__(self, topmodule, terms, binddict, resolved_terms, resolved_binddict, constlist):
VerilogDataflowMerge.__init__(self, topmodule, terms, binddict, resolved_terms, resolved_binddict, constlist)