Exemplo n.º 1
0
    def map(self, softPkg):
        dict = PullComponentGenerator.map(self, softPkg)
        
        dict['hasHwLoadRequestProp'] = False
        dict['hasHwLoadStatusProp'] = False
        for prop in dict['properties']:
            if prop.has_key('structdef'):
                if str(prop['structdef']['cpptype']) == "hw_load_request_struct":
                    dict['hasHwLoadRequestProp'] = True
                if str(prop['structdef']['cpptype']) == "hw_load_status_struct":
                    dict['hasHwLoadStatusProp'] = True
                    

        return dict
Exemplo n.º 2
0
    def map(self, softPkg):
        dict = PullComponentGenerator.map(self, softPkg)

        dict['hasHwLoadRequestProp'] = False
        dict['hasHwLoadStatusProp'] = False
        for prop in dict['properties']:
            if prop.has_key('structdef'):
                if str(prop['structdef']
                       ['cpptype']) == "hw_load_request_struct":
                    dict['hasHwLoadRequestProp'] = True
                if str(prop['structdef']
                       ['cpptype']) == "hw_load_status_struct":
                    dict['hasHwLoadStatusProp'] = True

        return dict
Exemplo n.º 3
0
    def map(self, softpkg):
        component = PullComponentGenerator.map(self, softpkg)

        # Create a list of varargin inputs.  varargin inputs can be either
        # ports of properties.  Having a list allows us to sort a list
        # of varargin ports and properties by name, which allows us to
        # order the arguments correctly when passing them to the feval call
        # in the code template.
        component['vararginList'] = []

        if component.has_key('properties'):
            for property in component['properties']:
                if property['cppname'].find("varargin") == 0:
                    component['vararginList'].append(property['cppname'])
        if component.has_key('ports'):
            for port in component['ports']:
                if port['cppname'].find("varargin") == 0:
                    component['vararginList'].append(port['cppname'])
        component['vararginList'].sort()

        return component