def MOD(i):
(x, y, z) = (data.block[i].out, data.block[i].in1, data.block[i].in2)
register_allocator.push("edx")
data.out.append("xor %edx, %edx")
try:
int(z)
data.zprime = z
reg = register_allocator.empty_reg(i, ["eax", "edx"])
data.out.append("mov $" + z + ", %" + reg)
data.zprime = reg
except:
if data.adesc[z] == "eax":
register_allocator.push(z)
register_allocator.getz(z)
pass
register_allocator.getreg(x, y, i, "eax")
try:
int(y)
data.yprime = y
except:
pass
register_allocator.gety(y)
data.out.append("idivl " + register_allocator.transform(data.zprime))
data.L = "edx"
register_allocator.update(x)
register_allocator.freereg(y, i)
register_allocator.freereg(z, i)
def DIV(i) :
(x, y, z) = (data.block[i].out, data.block[i].in1, data.block[i].in2)
register_allocator.push('edx')
data.out.append("xor %edx, %edx")
try :
int(z)
reg = register_allocator.empty_reg(['edx', 'eax'], i)
data.out.append('mov $' + z + ", %" + reg)
data.zprime = reg
except :
if data.adesc[z] == 'eax':
register_allocator.push(z)
register_allocator.getz(z)
pass
register_allocator.getreg(x, y, i, 'eax')
try :
int(y)
data.yprime = y
except :
pass
register_allocator.gety(y)
data.out.append("idivl " + register_allocator.transform(data.zprime))
register_allocator.update(x)
register_allocator.freereg(y, i)
register_allocator.freereg(z, i)
def ASSIGN(i):
(x, y) = (data.block[i].out, data.block[i].in1)
register_allocator.getreg(x, y, i)
try:
int(y)
data.yprime = y
except:
pass
register_allocator.gety(y)
register_allocator.update(x)
register_allocator.freereg(y, i)
def LOAD_ARRAY(i):
(x, y, z) = (data.block[i].out, data.block[i].in1, data.block[i].in2)
k = register_allocator.empty_reg(i)
try:
int(z)
pass
except:
register_allocator.getz(z)
if data.zprime == None:
data.zprime = z
data.out.append("movl " + register_allocator.transform(data.zprime) + ", " + register_allocator.transform(k))
data.L = k
data.out.append("movl " + y + "(, %" + k + ", 4), %" + k)
register_allocator.update(x)
def ADD(i):
(x, y, z) = (data.block[i].out, data.block[i].in1, data.block[i].in2)
try:
int(z)
data.zprime = z
except:
register_allocator.getz(z)
pass
register_allocator.getreg(x, y, i)
try:
int(y)
data.yprime = y
except:
pass
register_allocator.gety(y)
data.out.append("addl " + register_allocator.transform(data.zprime) + ", " + register_allocator.transform(data.L))
register_allocator.update(x)
register_allocator.freereg(y, i)
register_allocator.freereg(z, i)
