def __init__(self):
self.taken = Signal(reset=0)
self.pre = Registers()
self.post = Registers()
self.addresses_written = Signal(3, reset=0)
self.write_addr = Array([Signal(16) for _ in range(8)])
self.write_data = Array([Signal(8) for _ in range(8)])
self.addresses_read = Signal(3, reset=0)
self.read_addr = Array([Signal(16) for _ in range(8)])
self.read_data = Array([Signal(8) for _ in range(8)])
def __init__(self, tcpath, modelpath):
self._compiler = Compiler(None, None, tcpath)
self._gem5 = Gem5([], None)
self._exts = None
self._models = []
self._regs = Registers()
self._modelpath = modelpath
self._tcpath = tcpath
def __init__(self, **kwargs):
self._cached_data = {}
self.exposed_is_locked = None
super().__init__(Parameters)
from registers import Registers
self.registers = Registers(**kwargs)
self.registers.connect(self, self.parameters)
def __init__(self, program, mode = "MIPS"):
super(Assembler, self).__init__()
try: text = program.read()
except AttributeError: text = program
self.mode = mode.upper()
self.registers = Registers(self.mode)
lines = text.split("\n")
lines = clean(lines, self.mode)
instrs, data = split_sections(lines)
self.memory = Memory()
for d in data: self.memory.insert(d)
instrs = preprocess(instrs, self.mode)
self.labels = label_positions(instrs)
self.instructions = [Instruction(instr) for instr in instrs]
def __init__(self, img_spec, octant_key, bin_min_exp, bin_max_exp,
num_bins):
self._img_spec = img_spec
self._octant_key = octant_key
self._to_first_octant_scalars = [-1 if e else 1 for e in octant_key]
self._edge = self._log10_edges(bin_min_exp,
bin_max_exp,
num_bins=num_bins)
self.samples_in_octant = 0
self.hist3d = np.zeros((num_bins, num_bins, num_bins), dtype=np.uint)
self._label = self.label()
register_desc = f"registers for octant {self._label}"
self._registers = Registers(register_desc, self._label,
self._img_spec.channelnames)
def setUp(self):
patcher1 = patch.object(Registers, 'parse_instruction')
self.mock_parse = patcher1.start()
patcher2 = patch.object(Registers, 'is_true')
self.mock_is_true = patcher2.start()
patcher3 = patch.object(Registers, 'execute_instruction')
self.mock_execute = patcher3.start()
self.registers = Registers()
self.mock_parse.return_value = sentinel.code, sentinel.comparison
self.addCleanup(patcher1.stop)
self.addCleanup(patcher2.stop)
self.addCleanup(patcher3.stop)
def __init__(self, part="MSP430iua"):
assert part in CPU.CPU_TABLE
# Memoria de programa: Termina en el final del espacio de 65kB,
# y se reserva hacia abajo.
self.ROM = Memory(mem_size=self.CPU_TABLE[part][0],
mem_start=2**16 - self.CPU_TABLE[part][0],
readonly=True)
self.ROM.store_word_at(65534, self.ROM.mem_start)
# RAM inicia siempre en 0x200
self.RAM = Memory(mem_size=self.CPU_TABLE[part][1],
mem_start=0x0200,
readonly=False)
self.reg = Registers()
self.sim = Simulator(self.ROM, self.reg)
def __init__(self):
self.cmds = {
'ADD': self.add,
'ADDU': self.add,
'SUB': self.add,
'SUBU': self.add,
'OR': self.add,
'AND': self.add,
'NOR': self.add,
'XOR': self.add,
'ADDI': self.addi,
'ADDIU': self.addi,
'SUBI': self.addi,
'SUBIU': self.addi,
'ANDI': self.addi,
'ORI': self.addi,
'XORI': self.addi,
'LI': self.li,
'MOVE': self.move,
'SLT': self.slt,
'SLTU': self.slt,
'SLTI': self.slti,
'SLTIU': self.slti,
'SLL': self.sll,
'SRL': self.sll,
'J': self.j,
'JAL': self.jal,
'JR': self.jr,
'BEQ': self.beq,
'BNE': self.beq,
'MULT': self.mult,
'MULTU': self.mult,
'DIV': self.div,
'DIVU': self.div,
'MFLO': self.mfhi,
'MFHI': self.mfhi,
'NOP': self.nop,
'PYEVAL': self.pyeval,
'PYJAL': self.pycall,
'SYSCALL': self.pysyscall,
'PYEXEC': self.pyexec,
'LW': self.lw,
'SW': self.lw,
}
self.regs = Registers()
self.mem = Memory(32)
def __init__(self, verification: Instruction = None):
self.enable = Signal(reset=1)
self.addr = Signal(16)
self.din = Signal(8)
self.dout = Signal(8)
self.RWB = Signal(reset=1) # 1 = read, 0 = write
# registers
self.reg = Registers()
self.tmp = Signal(8) # temp signal when reading 16 bits
# internal exec state
self.opcode = Signal(8)
self.cycle = Signal(4, reset=1)
# formal verification
self.verification = verification
self.snapshot = Snapshot()
def test_example(self):
example_data = '\n'.join(['b inc 5 if a > 1',
'a inc 1 if b < 5',
'c dec -10 if a >= 1',
'c inc -20 if c == 10',
''])
try:
with tempfile.NamedTemporaryFile(mode='w', delete=False) as f:
f.write(example_data)
registers = Registers()
registers.parse_file(f.name)
finally:
os.remove(f.name)
self.assertEqual(registers.registers, {'a': 1, 'c': -10})
self.assertEqual(registers.get_largest_value(), 1)
self.assertEqual(registers.get_largest_value_ever_held(), 10)
def main():
from registers import Registers
m = Memory(1024, mem_start=0xfc00)
r = Registers()
s = Simulator(m, r)
m.store_words_at(0xfd00, [
0x3c55, 0x3e55, 0x1005, 0x1015, 0x0019, 0x1026, 0x1037, 0x1088, 0x1098,
0x001a, 0x10a9, 0x10b9, 0x1105, 0x1196, 0x001b, 0x122b, 0x12bc, 0x1300
])
m.store_word_at(0xfffe, 0xfd00)
print(str(m))
newpc = s.one_step(0xfffe)
print("%04x" % newpc)
newpc = s.one_step(newpc)
print("%04x" % newpc)
return 0
def __init__(self, path, most_neg=2, least_neg=-4, num_bins=None):
if not num_bins:
num_bins = 1 + most_neg - least_neg
self._path = path
self._img_size = self._path.stat().st_size
self._image_input = ImageInput.open(str(self._path))
if self._image_input is None:
# TODO check that the problem *is* actually the file is not there
raise FileNotFoundError(
f"could not read image `{self._path}': {oiio.geterror()}")
roi = self._image_input.spec().roi
# n.b. ROI xend and yend are range-style 'one beyond the end' values
self._x = roi.xbegin
self._width = roi.xend - roi.xbegin
self._y = roi.ybegin
self._height = roi.yend - roi.ybegin
self._overall_registers = Registers(
f"rewgisters for entire image",
self._image_input.spec().channelnames)
self.octants = {}
for octant in Octant.octant_keys():
self.octants[octant] = Octant(self._image_input.spec(), octant,
most_neg, least_neg, num_bins)
from registers import Registers
# https://c9x.me/x86/html/file_module_x86_id_147.html
def jmp(state, inst):
parts = inst.split(' ')
op = parts[0]
dst = int(parts[1], 16)
# Faking this since we don't really care for the examples we have
state.eip == dst
return state
if __name__ == "__main__":
s = Solver()
state = Registers()
state.eip = 0x1234
state = jmp(state, 'jmp 0x41414141')
s.add(state.eip == 0x41414141)
print('eip = 0x1234, jmp 0x41414141, eip == 0x41414141?')
check = s.check()
print(check)
print("eip == {}".format(state.eip))
s = Solver()
state = Registers()
state.eip = 0x41414141
state = jmp(state, 'jmp 0x42424242')
s.add(state.eip == 0x41414141)
check = s.check()
print('eip = 0x41414141, jmp 0x42424242, eip == 0x41414141?')
#!python
# imports do sistema do python
import sys
import re
# criados por nos
from instructions import Instructions
from registers import Registers
instr = Instructions()
regs = Registers()
# parse dos registradores
def parse_immediate(line):
line = line.split()
for i, token in enumerate(line):
# ignore a instrucao e os registradores,
# processe somente numeros decimais
# (imediatos e numeros crus)
if (i == 0 or token[0] == 'r'):
continue
# verifique o tamanho final das palavra
word_size = (5 if i < 3 else 16)
# altere o token (que e um numero)
token = bin(int(token))[2:]
# faca o prepend de zeros na frente do token pra que
# ele tenha o tamanho correto
line[i] = '0' * (word_size - len(token)) + token
return ' '.join(line)
def __init__(self, dmem, imem=None):
self.r = Registers(dmem.size())
self.dmem = dmem
self.imem = imem
args = OpArgs(first_arg,
second_arg,
OpType.REG,
OpType.IMM)
if len(list(filter(lambda g: g, match.groups()))) == 1:
return (instruction, None)
return (instruction, args)
cpu = CPU(MEMORY, Registers(AH=0, AL=0,
BH=0, BL=0,
CH=0, CL=0,
DH=0, DL=0,
SI=0, DI=0,
SP=0, BP=0,
FLAGS=Flags(CF=0, PF=0, AF=0,
ZF=0, SF=0, TF=0,
IF=0, DF=0, OF=0)))
print('CPU is initialized')
print(cpu)
history = []
while True:
instruction = input('Instruction$ ')
if instruction == 'history':
for i, entry in enumerate(history):
print(i, entry)
continue
from loadStation import LoadStation
from storeStation import StoreStation
from registers import Registers
from register import Register
from threading import Thread
from time import sleep
import string
import os
from tabulate import tabulate
multiplicationStation = MultiplicationStation(3)
divisionStation = DivisionStation(2)
additionStation = AdditionStation(4)
loadStation = LoadStation(6)
storeStation = StoreStation(6)
registers = Registers(10)
registersInt = Registers(10)
instructions = ['LD F4,0(R0)','LD F6,2(R0)','LD F7,4(R0)','LD F3,8(R0)', 'MULTD F2,F4,F6', 'MULTD F5,F7,F3','MULTD F8,F2,F5', 'MULTD F3,F5,F7', 'DIVD F9,F2,F6', 'ADDD F6,F8,F2', 'SD F2,0(F1)']
pc = 0
instructionInBus = False
def main():
global pc
for i in range(100):
raw_input("presione enter para generar un clock")
os.system('clear')
cdbThread = Thread(target = CDBThread)
instructioneFetcherThread = Thread(target = instructionFetcher)
instructioneFetcherThread.start()
cdbThread.start()
pc += 1
def test_init_creates_registers(self):
self.assertNotIn('registers', Registers.__dict__)
registers = Registers()
self.assertIsInstance(registers.registers, dict)
def setUp(self):
self.registers = Registers()