def main():
parser = common.ArgumentParser(
description="LiteX SoC on DDR4 Datacenter Test Board",
sys_clk_freq='50e6',
module='MTA18ASF2G72PZ')
g = parser.add_argument_group(title="DDR4 Datacenter Test Board")
parser.add(g,
"--eth-reset-time",
default="10e-3",
help="Duration of Ethernet PHY reset")
parser.add(g,
"--iodelay-clk-freq",
default="200e6",
help="IODELAY clock frequency")
vivado_build_args(g)
args = parser.parse_args()
soc_kwargs = common.get_soc_kwargs(args)
soc = SoC(**soc_kwargs)
target_name = 'ddr4_datacenter_test_board'
builder_kwargs = common.get_builder_kwargs(args, target_name=target_name)
builder = Builder(soc, **builder_kwargs)
build_kwargs = vivado_build_argdict(args) if not args.sim else {}
common.run(args, builder, build_kwargs, target_name=target_name)
def main():
parser = common.ArgumentParser(
description="LiteX SoC on Arty A7",
sys_clk_freq='100e6',
module='MT41K128M16',
)
g = parser.add_argument_group(title="Arty A7")
parser.add(g,
"--toolchain",
default="vivado",
choices=['vivado', 'symbiflow'],
help="Gateware toolchain to use")
parser.add(g,
"--variant",
default="a7-35",
choices=['a7-35', 'a7-100'],
help="FPGA variant")
vivado_build_args(g)
args = parser.parse_args()
soc_kwargs = common.get_soc_kwargs(args)
soc = SoC(variant=args.variant, toolchain=args.toolchain, **soc_kwargs)
target_name = 'arty'
builder_kwargs = common.get_builder_kwargs(args, target_name=target_name)
builder = Builder(soc, **builder_kwargs)
build_kwargs = vivado_build_argdict(args) if not args.sim else {}
common.run(args, builder, build_kwargs, target_name=target_name)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on ZCU104")
common.parser_args(parser, sys_clk_freq='125e6', module='MTA4ATF51264HZ')
vivado_build_args(parser)
args = parser.parse_args()
soc_kwargs = common.get_soc_kwargs(args)
soc = SoC(**soc_kwargs)
target_name = 'zcu104'
builder_kwargs = common.get_builder_kwargs(args, target_name=target_name)
builder = Builder(soc, **builder_kwargs)
build_kwargs = vivado_build_argdict(args) if not args.sim else {}
common.run(args, builder, build_kwargs, target_name=target_name)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
parser.add_argument("--toolchain",
default="vivado",
choices=['vivado', 'symbiflow'],
help="Gateware toolchain to use (default=vivado)")
common.parser_args(parser, sys_clk_freq='100e6', module='MT41K128M16')
vivado_build_args(parser)
args = parser.parse_args()
soc_kwargs = common.get_soc_kwargs(args)
soc = SoC(toolchain=args.toolchain, **soc_kwargs)
target_name = 'arty'
builder_kwargs = common.get_builder_kwargs(args, target_name=target_name)
builder = Builder(soc, **builder_kwargs)
build_kwargs = vivado_build_argdict(args) if not args.sim else {}
common.run(args, builder, build_kwargs, target_name=target_name)
def main():
parser = common.ArgumentParser(description="LiteX SoC on ZCU104",
sys_clk_freq='125e6',
module='MTA4ATF51264HZ')
g = parser.add_argument_group(title="ZCU104")
g.add_argument(
"--iodelay-clk-freq",
type=float,
help="Use given exact IODELAYCTRL reference clock frequency")
vivado_build_args(g)
args = parser.parse_args()
soc_kwargs = common.get_soc_kwargs(args)
soc = SoC(**soc_kwargs)
target_name = 'zcu104'
builder_kwargs = common.get_builder_kwargs(args, target_name=target_name)
builder = Builder(soc, **builder_kwargs)
build_kwargs = vivado_build_argdict(args) if not args.sim else {}
common.run(args, builder, build_kwargs, target_name=target_name)