def _test_model(cls):
A = cls()
A.elaborate()
simple_sim_pass(A, 0x123)
for i in xrange(10):
A.tick()
def test_write_two_slices_and_bit():
class Top(ComponentLevel3):
def __init__(s):
s.A = Wire(Bits32)
@s.update
def up_wr_0_16():
s.A[0:16] = Bits16(0xff)
@s.update
def up_wr_16_30():
s.A[16:30] = Bits14(0xff)
@s.update
def up_wr_30_31():
s.A[30] = Bits1(1)
@s.update
def up_rd_A():
print s.A[0:17]
m = Top()
m.elaborate()
simple_sim_pass(m, 0x123)
assert len(m._all_constraints) == 2
_, x = list(m._all_constraints)[0]
_, y = list(m._all_constraints)[1]
# two constraints are: up_wr_0_16 < up_rd_A and up_wr_16_30 < up_rd_A
assert m._all_id_upblk[x].__name__ == "up_rd_A" and \
m._all_id_upblk[y].__name__ == "up_rd_A"
def test_wr_As_rd_A_rd_At_bit_cannot_schedule():
class Top(ComponentLevel3):
def __init__(s):
s.A = Wire(Bits32)
@s.update
def up_wr_As():
s.A[0:16] = Bits16(0x1234)
@s.update
def up_rd_A():
z = s.A
@s.update
def up_rd_At():
assert s.A[16] == 0
m = Top()
m.elaborate()
simple_sim_pass(m, 0x123)
assert len(m._all_constraints) == 1
x, y = list(m._all_constraints)[0]
assert m._all_id_upblk[x].__name__ == "up_wr_As" and \
m._all_id_upblk[y].__name__ == "up_rd_A" # only one constraint
def test_connect_rd_As_wr_x_conn_At_disjoint():
class Top(ComponentLevel3):
def __init__(s):
s.x = Wire(Bits24)
s.A = Wire(Bits32)
s.connect(s.A[0:24], s.x)
@s.update
def up_wr_x():
s.x = Bits24(0x123456)
@s.update
def up_rd_As():
assert s.A[24:32] == 0
m = Top()
m.elaborate()
simple_sim_pass(m, 0x123)
assert len(m._all_constraints) == 1
x, y = list(m._all_constraints)[0]
assert m._all_id_upblk[x].__name__ == "up_wr_x" and \
m._all_id_upblk[y].__name__ == "_x" # connection block
def test_write_two_disjoint_slices_no_reader():
class Top(ComponentLevel3):
def __init__(s):
s.A = Wire(Bits32)
@s.update
def up_wr_0_16():
s.A[0:16] = Bits16(0xff)
@s.update
def up_wr_16_30():
s.A[16:30] = Bits14(0xff)
@s.update
def up_rd_17_30():
assert s.A[16:30] == 0xff
m = Top()
m.elaborate()
simple_sim_pass(m, 0x123)
assert len(m._all_constraints) == 1
x, y = list(m._all_constraints)[0]
assert m._all_id_upblk[x].__name__ == "up_wr_16_30" and \
m._all_id_upblk[y].__name__ == "up_rd_17_30" # only one constraint
def test_wr_A_b_rd_A_rd_A_a_cannot_schedule():
class Top( ComponentLevel3 ):
def __init__( s ):
s.A = Wire( SomeMsg() )
@s.update
def up_wr_A_b():
s.A.b = Bits32( 123 )
@s.update
def up_rd_A():
z = s.A
@s.update
def up_rd_A_a():
assert s.A.a == 12
m = Top()
m.elaborate()
simple_sim_pass( m, 0x123 )
assert len(m._all_constraints) == 1
x, y = list(m._all_constraints)[0]
assert m._all_id_upblk[x].__name__ == "up_wr_A_b" and \
m._all_id_upblk[y].__name__ == "up_rd_A" # only one constraint
def _test_model(cls):
A = cls()
A.elaborate()
simple_sim_pass(A, 0x123)
T, time = 0, 20
while not A.done() and T < time:
A.tick()
print A.line_trace()
T += 1
def _test_model(cls):
A = cls()
A.elaborate()
simple_sim_pass(A, 0x123)
while not A.done():
A.tick()
print A.line_trace()
simple_sim_pass(A, 0x1234)
while not A.done():
A.tick()
print A.line_trace()
def test_rd_As_wr_At_impl_disjoint():
class Top(ComponentLevel3):
def __init__(s):
s.A = Wire(Bits32)
@s.update
def up_wr_At():
s.A[16:32] = Bits16(0xff)
@s.update
def up_rd_As():
assert s.A[0:16] == 0
m = Top()
m.elaborate()
simple_sim_pass(m, 0x123)
assert len(m._all_constraints) == 0 # no constraint at all!
def test_reset():
class B(RTLComponent):
def __init__(s):
s.out = OutVPort(Bits32)
@s.update_on_edge
def up_out():
if s.reset:
s.out = Bits32(0x12345678)
else:
s.out = Bits32(0)
class Top(RTLComponent):
def __init__(s):
s.b = B()
@s.update
def up_tmp():
print s.b.out
top = Top()
top.elaborate()
simple_sim_pass(top, 0x123)
top.sim_reset()