def _discover_all(self):
"""When iterating or performing tab completion, we run through ahead of
time and discover all possible children, populating the ``_sub_handles``
mapping. Hierarchy can't change after elaboration so we only have to
do this once.
"""
if self._discovered: return
self._log.debug("Discovering all on %s", self._name)
iterator = simulator.iterate(self._handle, simulator.OBJECTS)
while True:
try:
thing = simulator.next(iterator)
except StopIteration:
# Iterator is cleaned up internally in GPI
break
name = simulator.get_name_string(thing)
try:
hdl = SimHandle(thing, self._child_path(name))
except TestError as e:
self._log.debug("%s" % e)
continue
key = self._sub_handle_key(name)
if not key is None:
self._sub_handles[key] = hdl
else:
self._log.debug("Unable to translate handle >%s< to a valid _sub_handle key" % hdl._name)
continue
self._discovered = True
def drivers(self):
"""
An iterator for gathering all drivers for a signal
"""
iterator = simulator.iterate(self._handle, simulator.DRIVERS)
while True:
yield SimHandle(simulator.next(iterator))
def loads(self):
"""
An iterator for gathering all loads on a signal
"""
iterator = simulator.iterate(self._handle, simulator.LOADS)
while True:
yield SimHandle(simulator.next(iterator))
def loads(self):
"""
An iterator for gathering all loads on a signal
"""
iterator = simulator.iterate(self._handle, simulator.LOADS)
while True:
yield SimHandle(simulator.next(iterator))
def drivers(self):
"""
An iterator for gathering all drivers for a signal
"""
iterator = simulator.iterate(self._handle, simulator.DRIVERS)
while True:
yield SimHandle(simulator.next(iterator))
def loads(self):
"""
An iterator for gathering all loads on a signal
"""
iterator = simulator.iterate(self._handle, simulator.LOADS)
while True:
# Path is left as the default None since handles are not derived from the hierarchy
yield SimHandle(simulator.next(iterator))
def input_dist(o1, o2):
i1, i2 = o1["input"], o2["input"]
eqns1 = inputs.input_as_lambdas(i1)
eqns2 = inputs.input_as_lambdas(i2)
syst1 = {"n": 2, "consts": [], "eqns": eqns1}
syst2 = {"n": 2, "consts": [], "eqns": eqns2}
test_iterates = constants.num_warmup_iterations + constants.num_measur_iterations
x1, x2 = [0, 0], [0, 0]
traj1, traj2 = [], []
for i in xrange(test_iterates):
traj1.append(x1)
traj2.append(x2)
x1 = simulator.iterate(syst1, x1)
x2 = simulator.iterate(syst2, x2)
diff = [(fabs(traj1[i][1] - traj2[i][1])) / test_iterates for i in xrange(len(traj1))]
dist = log(log(sqrt(sum(diff)) + 1) + 1)
return dist
def loads(self):
"""
An iterator for gathering all loads on a signal
"""
iterator = simulator.iterate(self._handle, simulator.LOADS)
while True:
# Path is left as the default None since handles are not derived from the hierarchy
yield SimHandle(simulator.next(iterator))
def drivers(self):
"""An iterator for gathering all drivers for a signal."""
try:
iterator = simulator.iterate(self._handle, simulator.DRIVERS)
while True:
# Path is left as the default None since handles are not derived from the hierarchy
yield SimHandle(simulator.next(iterator))
except GeneratorExit:
pass
def _discover_all(self):
"""
When iterating or performing tab completion, we run through ahead of
time and discover all possible children, populating the _sub_handle
mapping. Hierarchy can't change after elaboration so we only have to
do this once.
"""
if self._discovered: return
self._log.debug("Discovering all on %s", self._name)
iterator = simulator.iterate(self._handle, simulator.OBJECTS)
while True:
try:
thing = simulator.next(iterator)
except StopIteration:
# Iterator is cleaned up internally in GPI
break
name = simulator.get_name_string(thing)
try:
hdl = SimHandle(thing)
except TestError as e:
self._log.debug("%s" % e)
continue
# This is slightly hacky, but we want generate loops to result in a list
# These are renamed in VHPI to __X where X is the index
import re
result = re.match("(?P<name>.*)__(?P<index>\d+)$", name)
if not result:
result = re.match("(?P<name>.*)\((?P<index>\d+)\)$", name)
# Modelsim VPI returns names in standard form name[index]
if not result:
result = re.match("(?P<name>.*)\[(?P<index>\d+)\]$", name)
if result:
index = int(result.group("index"))
name = result.group("name")
if name not in self._sub_handles:
self._sub_handles[name] = []
self._log.debug("creating new group for %s", name)
if len(self._sub_handles[name]) < index + 1:
delta = index - len(self._sub_handles[name]) + 1
self._sub_handles[name].extend([None] * delta)
self._sub_handles[name][index] = hdl
self._log.debug("%s.%s[%d] is now %s", self._name, name, index,
hdl._name)
#for something in self._sub_handles[name]:
# self._log.debug("%s: %s" % (type(something), something))
else:
self._log.debug("%s didn't match an index pattern", name)
self._sub_handles[hdl._name.split(".")[-1]] = hdl
self._discovered = True
def _discover_all(self):
"""
When iterating or performing tab completion, we run through ahead of
time and discover all possible children, populating the _sub_handle
mapping. Hierarchy can't change after elaboration so we only have to
do this once.
"""
if self._discovered: return
self._log.debug("Discovering all on %s", self._name)
iterator = simulator.iterate(self._handle, simulator.OBJECTS)
while True:
try:
thing = simulator.next(iterator)
except StopIteration:
# Iterator is cleaned up internally in GPI
break
name = simulator.get_name_string(thing)
try:
hdl = SimHandle(thing)
except TestError as e:
self._log.debug("%s" % e)
continue
# This is slightly hacky, but we want generate loops to result in a list
# These are renamed in VHPI to __X where X is the index
import re
result = re.match("(?P<name>.*)__(?P<index>\d+)$", name)
if not result:
result = re.match("(?P<name>.*)\((?P<index>\d+)\)$", name)
# Modelsim VPI returns names in standard form name[index]
if not result:
result = re.match("(?P<name>.*)\[(?P<index>\d+)\]$", name)
if result:
index = int(result.group("index"))
name = result.group("name")
if name not in self._sub_handles:
self._sub_handles[name] = []
self._log.debug("creating new group for %s", name)
if len(self._sub_handles[name]) < index + 1:
delta = index - len(self._sub_handles[name]) + 1
self._sub_handles[name].extend([None]*delta)
self._sub_handles[name][index] = hdl
self._log.debug("%s.%s[%d] is now %s", self._name, name, index, hdl._name)
#for something in self._sub_handles[name]:
# self._log.debug("%s: %s" % (type(something), something))
else:
self._log.debug("%s didn't match an index pattern", name)
self._sub_handles[hdl._name.split(".")[-1]] = hdl
self._discovered = True
def __iter__(self):
"""Iterates over all known types defined by simulator module"""
for handle_type in [
simulator.MODULE, simulator.PARAMETER, simulator.REG,
simulator.NET, simulator.NETARRAY
]:
iterator = simulator.iterate(handle_type, self._handle)
while True:
try:
thing = simulator.next(iterator)
except StopIteration:
break
hdl = SimHandle(thing)
self._sub_handles[hdl.name] = hdl
yield hdl
def __iter__(self):
"""Iterates over all known types defined by simulator module"""
for handle_type in [simulator.MODULE,
simulator.PARAMETER,
simulator.REG,
simulator.NET,
simulator.NETARRAY]:
iterator = simulator.iterate(handle_type, self._handle)
while True:
try:
thing = simulator.next(iterator)
except StopIteration:
break
hdl = SimHandle(thing)
self._sub_handles[hdl.name] = hdl
yield hdl
def get_checkpoint_hier(entity):
iterator = simulator.iterate(entity._handle, simulator.OBJECTS)
while True:
try:
ii = simulator.next(iterator)
except StopIteration:
break
hdl = SimHandle(ii, entity._path + "." + simulator.get_name_string(ii))
if ((simulator.get_type(ii) is simulator.MODULE)
or (simulator.get_type(ii) is simulator.NETARRAY)
or (simulator.get_type(ii) is simulator.GENARRAY)):
get_checkpoint_hier(hdl)
elif simulator.get_type(ii) is simulator.REG:
checkpoint_hier.append(hdl)
def __init__(self, handle, mode):
self._iter = simulator.iterate(handle, mode)