def generate(self, **kargs):
StateTransition.registerStateTransitionHandler(
StateTransitionHandlerTest(self.genThread),
EStateTransitionType.Explicit,
(EStateElementType.GPR, EStateElementType.FloatingPointRegister))
# Test overwriting a StateTransitionHandler assignment
StateTransition.registerStateTransitionHandler(
StateTransitionHandlerTest(self.genThread),
EStateTransitionType.Explicit,
(EStateElementType.FloatingPointRegister, ))
state_elem_type_order = (EStateElementType.PredicateRegister,
EStateElementType.FloatingPointRegister,
EStateElementType.Memory,
EStateElementType.SystemRegister,
EStateElementType.GPR,
EStateElementType.VmContext,
EStateElementType.VectorRegister,
EStateElementType.PrivilegeLevel,
EStateElementType.PC)
StateTransition.setDefaultStateTransitionOrderMode(
EStateTransitionType.Boot,
EStateTransitionOrderMode.ByStateElementType,
state_elem_type_order)
StateTransition.setDefaultStateTransitionOrderMode(
EStateTransitionType.Explicit,
EStateTransitionOrderMode.AsSpecified)
state = self._createState()
StateTransition.transitionToState(state)
state_transition_test_utils.verifyState(self, self._mExpectedStateData)
def generate(self, **kargs):
state_trans_handler = PartialStateTransitionHandlerTest(self.genThread)
StateTransition.registerStateTransitionHandler(
state_trans_handler, EStateTransitionType.Explicit,
(EStateElementType.FloatingPointRegister, ))
state = self._createState()
StateTransition.transitionToState(state)
state_transition_test_utils.verifyState(self, self._mExpectedStateData)
def generate(self, **kargs):
for _ in range(3):
state = self._createState()
self._genRandomBranchInstructions()
StateTransition.transitionToState(state)
state_transition_test_utils.verifyState(self, self._mExpectedStateData)
self._genRandomBranchInstructions()
def generate(self, **kargs):
state = self._createState()
target_addr_range = '%d-%d' % (self._mMemBlockStartAddr,
self._mMemBlockEndAddr)
instructions = ('LD##RISCV', 'SD##RISCV')
for _ in range(RandomUtils.random32(2, 5)):
for _ in range(RandomUtils.random32(50, 100)):
self.genInstruction(self.choice(instructions),
{'LSTarget': target_addr_range})
StateTransition.transitionToState(state)
state_transition_test_utils.verifyState(self,
self._mExpectedStateData)
def generate(self, **kargs):
state = self._createState()
state_elem_type_order = (EStateElementType.VectorRegister,
EStateElementType.Memory,
EStateElementType.SystemRegister,
EStateElementType.FloatingPointRegister,
EStateElementType.PredicateRegister,
EStateElementType.GPR,
EStateElementType.VmContext,
EStateElementType.PrivilegeLevel,
EStateElementType.PC)
StateTransition.transitionToState(
state, EStateTransitionOrderMode.ByStateElementType,
state_elem_type_order)
state_transition_test_utils.verifyState(self, self._mExpectedStateData)
def generate(self, **kargs):
priv_level_names = ('U', 'S', None, 'M')
for priv_level in (1, 0, 1, 3):
state = State()
if RandomUtils.random32(0, 1) == 1:
state.addPrivilegeLevelStateElementByName(priv_level_names[priv_level])
else:
state.addPrivilegeLevelStateElement(priv_level)
self._mExpectedStateData[EStateElementType.PrivilegeLevel] = priv_level
StateTransition.transitionToState(state)
for _ in range(10):
self.genInstruction('ADDI##RISCV')
state_transition_test_utils.verifyState(self, self._mExpectedStateData)
def generate(self, **kargs):
# Disable floating point, so the StateTransition can enable it
sys_reg_name = 'misa'
(sys_reg_val, valid) = self.readRegister(sys_reg_name)
state_transition_test_utils.assertValidRegisterValue(
self, sys_reg_name, valid)
load_gpr64_seq = LoadGPR64(self.genThread)
rand_gpr_index = self.getRandomGPR(exclude='0')
load_gpr64_seq.load(rand_gpr_index, 0x0000028)
self.genInstruction(
'CSRRC#register#RISCV', {
'rd': 0,
'rs1': rand_gpr_index,
'csr': self.getRegisterIndex(sys_reg_name)
})
state = self._createState()
StateTransition.transitionToState(state,
EStateTransitionOrderMode.ByPriority)
state_transition_test_utils.verifyState(self, self._mExpectedStateData)
def generate(self, **kargs):
state_a = self._createStateA()
StateTransition.transitionToState(state_a,
EStateTransitionOrderMode.ByPriority)
state_transition_test_utils.verifyState(self, self._mExpectedStateData)
instructions = ('ADDI##RISCV', 'ADDW##RISCV', 'LUI##RISCV',
'SLLI#RV64I#RISCV', 'SRLI#RV64I#RISCV')
for _ in range(RandomUtils.random32(200, 500)):
self.genInstruction(self.choice(instructions))
state_b = self._createStateB()
StateTransition.transitionToState(state_b)
state_transition_test_utils.verifyState(self, self._mExpectedStateData)
for _ in range(RandomUtils.random32(200, 500)):
self.genInstruction('SD##RISCV')
state_c = self._createStateC()
StateTransition.transitionToState(state_c)
state_transition_test_utils.verifyState(self, self._mExpectedStateData)
for _ in range(RandomUtils.random32(200, 500)):
self.genInstruction('FMUL.D#Double-precision#RISCV')
def generate(self, **kargs):
state = self._createState()
StateTransition.transitionToState(state)
state_transition_test_utils.verifyState(self, self._mExpectedStateData)
