def power_opt_low_power_profile():
# If CPUID.06H:ECX.SETBH[bit 3] is set, then the processor supports
# performance-energy bias preference and IA32_ENERGY_PERF_BIAS (1B0H) MSR
setbh = (bits.cpuid(bits.bsp_apicid(),6).ecx >> 3) & 1
if not setbh:
return
testmsr.test_msr_consistency("Energy Performance Bias", 0x1b0, mask=0xf)
testmsr.test_msr("Energy Performance Bias 12-15", 0x1b0, expected_value=3, shift=2, mask=3)
def test_pm_generic_profile():
testmsr.test_msr_consistency("Max non-turbo ratio must be consistent",
0xce,
mask=0xff00)
testpci.test_pci("Bus master disable",
0,
31,
0,
0xa9,
bytes=1,
shift=2,
mask=1,
expected_value=1)
testmsr.test_msr("C1 Auto Undemotion Enable",
0xe2,
shift=28,
mask=1,
expected_value=1)
testmsr.test_msr("C3 Auto Undemotion Enable",
0xe2,
shift=27,
mask=1,
expected_value=1)
testmsr.test_msr("C1 Auto Demotion Enable",
0xe2,
shift=26,
mask=1,
expected_value=1)
testmsr.test_msr("C3 Auto Demotion Enable",
0xe2,
shift=25,
mask=1,
expected_value=1)
testmsr.test_msr("IO MWAIT Redirection Enable",
0xe2,
shift=10,
mask=1,
expected_value=1)
testmsr.test_msr("C1E Enable", 0x1fc, shift=1, mask=1, expected_value=1)
testmsr.test_msr("EIST Enable", 0x1a0, shift=16, mask=1, expected_value=1)
testmsr.test_msr("Turbo Enable", 0x1a0, shift=38, mask=1, expected_value=0)
testmsr.test_msr("EIST Hardware Coordination Enable",
0x1aa,
mask=1,
expected_value=0)
testmsr.test_msr_consistency("IO Capture C-state Range Consistent",
0xe4,
shift=16,
mask=7)
io_capture_range, io_capture_range_str = testmsr.MSR(
"IO Capture C-state Range", bits.bsp_apicid(), 0xe4, 18, 16)
testsuite.test("IO Capture C-state Range <= 2", io_capture_range <= 2)
testsuite.print_detail(io_capture_range_str)
def power_opt_low_power_profile():
# If CPUID.06H:ECX.SETBH[bit 3] is set, then the processor supports
# performance-energy bias preference and IA32_ENERGY_PERF_BIAS (1B0H) MSR
setbh = (bits.cpuid(bits.bsp_apicid(), 6).ecx >> 3) & 1
if not setbh:
return
testmsr.test_msr_consistency("Energy Performance Bias", 0x1b0, mask=0xf)
testmsr.test_msr("Energy Performance Bias 12-15",
0x1b0,
expected_value=3,
shift=2,
mask=3)
def test_pm_generic_profile():
testmsr.test_msr_consistency("Max non-turbo ratio must be consistent", 0xce, mask=0xff00)
testpci.test_pci("Bus master disable", 0, 31, 0, 0xa9, bytes=1, shift=2, mask=1, expected_value=1)
testmsr.test_msr("C1 Auto Demotion Enable", 0xe2, shift=26, mask=1, expected_value=1)
testmsr.test_msr("C3 Auto Demotion Enable", 0xe2, shift=25, mask=1, expected_value=1)
testmsr.test_msr("IO MWAIT Redirection Enable", 0xe2, shift=10, mask=1, expected_value=1)
testmsr.test_msr("C1E Enable", 0x1fc, shift=1, mask=1, expected_value=1)
testmsr.test_msr("EIST Enable", 0x1a0, shift=16, mask=1, expected_value=1)
testmsr.test_msr("Turbo Enable", 0x1a0, shift=38, mask=1, expected_value=0)
testmsr.test_msr("EIST Hardware Coordination Enable", 0x1aa, mask=1, expected_value=0)
testmsr.test_msr_consistency("IO Capture C-state Range Consistent", 0xe4, shift=16, mask=7)
io_capture_range, io_capture_range_str = testmsr.MSR("IO Capture C-state Range", bits.bsp_apicid(), 0xe4, 18, 16)
testsuite.test("IO Capture C-state Range <= 2", io_capture_range <= 2)
testsuite.print_detail(io_capture_range_str)
def test_smrr():
"""Test the SMRR-related configuration"""
cpus = sorted(bits.cpus())
if not testmsr.test_msr_consistency(
text="IA32_MTRRCAP Bit [11] (SMRR Supported) must be consistent", first_msr=0xFE, shift=11, mask=1
):
return
ia32_mtrrcap = bits.rdmsr(cpus[0], 0xFE)
if ia32_mtrrcap is not None and not ia32_mtrrcap & (1 << 11):
return
if testmsr.msr_available(0x1F2) and testmsr.msr_available(0x1F3):
MSR_SMRR_PHYS_BASE = 0x1F2
MSR_SMRR_PHYS_MASK = 0x1F3
elif testmsr.msr_available(0xA0) and testmsr.msr_available(0xA1):
MSR_SMRR_PHYS_BASE = 0xA0
MSR_SMRR_PHYS_MASK = 0xA1
return
else:
return
testmsr.test_msr_consistency(
text="SMRR must be consistent across all processors", first_msr=MSR_SMRR_PHYS_BASE, last_msr=MSR_SMRR_PHYS_MASK
)
for apicid in cpus:
smrr_physbase, smrr_physbase_str = testmsr.MSR("SMRR Physbase", apicid, MSR_SMRR_PHYS_BASE, 31, 12)
smrr_type, smrr_type_str = testmsr.MSR("SMRR Type", apicid, MSR_SMRR_PHYS_BASE, 2, 0)
smrr_physmask, smrr_physmask_str = testmsr.MSR("SMRR Physmask", apicid, MSR_SMRR_PHYS_MASK, 31, 12)
smrr_valid, smrr_valid_str = testmsr.MSR("SMRR Valid", apicid, MSR_SMRR_PHYS_MASK, 11, 11)
testsuite.test("SMRR_PHYSBASE must be aligned on an 8MB boundary", (smrr_physbase % 0x800) == 0)
testsuite.print_detail(smrr_physbase_str)
testsuite.print_detail("SMRR_PHYSBASE % 0x800 must be 0")
testsuite.test("SMRR Type must be Write-Back (Best performance)", smrr_type == 6)
testsuite.print_detail(smrr_type_str)
testsuite.print_detail("SMRR Type must be 6")
testsuite.test("SMRR size must be at least 8MB", smrr_physmask >= 0x800)
testsuite.print_detail(smrr_physmask_str)
testsuite.print_detail("SMRR Physmask must be >= 0x800")
testsuite.test("SMRR Valid bit must be 1", smrr_valid)
testsuite.print_detail(smrr_valid_str)
def cmd_test_msr_consistency(args):
return testmsr.test_msr_consistency(**vars(args))
