def test_arbiter(self):
f, res = parseFile("arbiter.v", VERILOG)
str(res)
a = self.find_obj_by_name(res, HdlModuleDec, "arbiter")
self.assertEqual(len(a.params), 0)
self.assertEqual(len(a.ports), 10)
ports = {
"clk": HdlDirection.IN,
"rst": HdlDirection.IN,
"req3": HdlDirection.IN,
"req2": HdlDirection.IN,
"req1": HdlDirection.IN,
"req0": HdlDirection.IN,
"gnt3": HdlDirection.OUT,
"gnt2": HdlDirection.OUT,
"gnt1": HdlDirection.OUT,
"gnt0": HdlDirection.OUT,
}
_ports = {p.name: p.direction for p in a.ports}
self.assertDictEqual(_ports, ports)
def test_include(self):
f, res = parseFile("include.v", VERILOG)
str(res)
self.check_obj_names(res, HdlModuleDec, ["arbiter", "uart"])
def test_fifo_rx(self):
f, res = parseFile("fifo_rx.v", VERILOG)
f = self.find_obj_by_name(res, HdlModuleDec, "fifo_rx")
self.assertEqual(len(f.params), 2)
self.assertEqual(len(f.ports), 11)
str(res)
def test_system_verilog_mem_base_object(self):
f, res = parseFile("mem_base_object.sv", SV)
str(res)
def test_directive_verilogpp(self):
f, res = parseFile("directive_verilogpp.v", VERILOG)
str(res)
def test_verilog_macro(self):
f, res = parseFile("macro.v", VERILOG)
str(res)
def test_verilog_define(self):
f, res = parseFile("define.v", VERILOG)
str(res)
def test_verilog_adder_implicit(self):
f, res = parseFile("adder_implicit.v", VERILOG)
str(res)
def test_crc_functions(self):
f, res = parseFile("crc_functions.sv", SV)
str(res)